参数资料
型号: FDMC8200S
厂商: Fairchild Semiconductor
文件页数: 2/12页
文件大小: 0K
描述: MOSFET N-CH DUAL 30V 8MLP
标准包装: 1
系列: PowerTrench®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 6A
开态Rds(最大)@ Id, Vgs @ 25° C: 20 毫欧 @ 6A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 10nC @ 10V
输入电容 (Ciss) @ Vds: 660pF @ 15V
功率 - 最大: 2.5W
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘
供应商设备封装: 8-MLP(3.3X3.3),Power33
包装: 标准包装
其它名称: FDMC8200SDKR
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DS S
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 1mA, V GS = 0 V
I D = 250 μ A, referenced to 25°C
I D = 1mA, referenced to 25°C
V DS = 24 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
30
30
14
13
1
500
100
100
V
mV/°C
μ A
nA
nA
On Characteristics
V GS(th)
Δ V GS(th)
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
V GS = V DS , I D = 1mA
I D = 250 μ A, referenced to 25°C
I D = 1mA, referenced to 25°C
Q1
Q2
Q1
Q2
1.0
1.0
2.3
2.0
-5
-6
3.0
3.0
V
mV/°C
V GS = 10 V, I D = 6 A
16
20
V GS = 4.5 V, I D = 5 A
Q1
24
32
r DS(on)
Static Drain to Source On Resistance
V GS = 10 V, I D = 6 A, T J = 125°C
V GS = 10 V, I D = 8.5 A
V GS = 4.5 V, I D = 7.2 A
Q2
22
7.8
10.3
28
10.0
13.5
m Ω
V GS = 10 V, I D = 8.5 A, T J = 125°C
11.4
13.1
g FS
Forward Transconductance
V DD = 5 V, I D = 6 A
V DD = 5 V, I D = 8.5 A
Q1
Q2
29
43
S
Dynamic Characteristics
C iss
Input Capacitance
Q1
Q2
495
1080
660
1436
pF
C oss
C rss
Output Capacitance
Reverse Transfer Capacitance
V DS = 15 V, V GS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
145
373
20
35
195
495
30
52
pF
pF
R g
Gate Resistance
Q1
Q2
0.2
0.2
1.4
1.2
4.2
3.6
Ω
Switching Characteristics
t d(on)
t r
t d(off)
t f
Q g(TOT)
Q g(TOT)
Q gs
Q gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Q1
V DD = 15 V, I D = 1 A,
V GS = 10 V, R GEN = 6 Ω
Q2
V DD = 15 V, I D = 1 A,
V GS = 10 V, R GEN = 6 Ω
V GS = 0 V to 10 V Q1
V DD = 15 V,
V GS = 0 V to 4.5 V I D = 6 A
Q2
V DD = 15 V
I D = 8.5 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
11
7.6
3.1
1.8
35
21
1.3
8.5
7.3
15.7
3.1
7.2
1.8
3
1
1.9
20
15
10
10
56
34
10
17
10
22
4.3
10
ns
ns
ns
ns
nC
nC
nC
nC
?2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
2
www.fairchildsemi.com
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