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| 型号： | FDMC8200S |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH DUAL 30V 8MLP |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | 2 个 N 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 30V |
| 电流 - 连续漏极(Id) @ 25° C： | 6A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 20 毫欧 @ 6A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 10nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 660pF @ 15V |
| 功率 - 最大： | 2.5W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-MLP（3.3X3.3），Power33 |
| 包装： | 标准包装 |
| 其它名称： | FDMC8200SDKR |
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V GS = 0 V, I S = 6 A
(Note 2)
Q1
0.8
1.2
V SD
Source-Drain Diode Forward Voltage V GS = 0 V, I S = 8.5 A
V GS = 0 V, I S = 1.3 A
(Note 2)
(Note 2)
Q2
Q2
0.8
0.6
1.2
0.8
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
Q1
I F = 6 A, di/dt = 100 A/s
Q2
I F = 8.5 A, di/dt = 300 A/s
Q1
Q2
Q1
Q2
13
20
2.3
15
24
32
10
24
ns
nC
Notes:
1. R θ JA is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined
by the user's board design.
a.65 °C/W when mounted on
a 1 in 2 pad of 2 oz copper
c. 180 °C/W when mounted on a
minimum pad of 2 oz copper
b.50 °C/W when mounted on
a 1 in 2 pad of 2 oz copper
d. 125 °C/W when mounted on a
minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3.Starting Q1: T = 25 ° C, L = 1 mH, I = 5 A, Vgs = 10V, Vdd = 27V, 100% test at L = 3 mH, I = 4 A; Q2: T = 25 ° C, L = 1 mH, I = 8 A, Vgs = 10V, Vdd = 27V,
100% test at L = 3 mH, I = 3.2 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
?2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
3
www.fairchildsemi.com
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