Contents
Paragraph
Number
Title
Page
Number
x
G2 PowerPC Core Reference Manual
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MOTOROLA
4.4.2
4.4.3
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.5.1
4.6.5.2
4.6.5.3
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.4.1
4.7.5
4.7.6
4.7.7
4.7.8
4.7.9
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.8.8
4.8.9
4.9
4.10
4.11
4.12
4.12.1
Data Cache Cast-Out Operation ......................................................................4-9
Cache Block Push Operation...........................................................................4-9
Data Cache Transactions on Bus .........................................................................4-9
Single-Beat Transactions.................................................................................4-9
Burst Transactions ...........................................................................................4-9
Access to Direct-Store Segments...................................................................4-10
Memory Management/Cache Access Mode Bits—W, I, M, and G...................4-10
Write-Through Attribute (W) ........................................................................ 4-11
Caching-Inhibited Attribute (I)......................................................................4-12
Memory Coherency Attribute (M).................................................................4-12
Guarded Attribute (G)....................................................................................4-13
W, I, and M Bit Combinations.......................................................................4-13
Out-of-Order Execution and Guarded Memory ........................................4-14
Effects of Out-of-Order Data Accesses.....................................................4-14
Effects of Out-of-Order Instruction Fetches..............................................4-15
Cache Coherency—MEI Protocol.....................................................................4-15
MEI State Definitions....................................................................................4-16
MEI State Diagram........................................................................................4-16
MEI Hardware Considerations ......................................................................4-17
Coherency Precautions ..................................................................................4-19
Coherency in Single-Processor Systems ...................................................4-19
Load and Store Coherency Summary............................................................4-19
Atomic Memory References..........................................................................4-20
Cache Reaction to Specific Bus Operations..................................................4-20
Operations Causing core_artry Assertion......................................................4-21
Enveloped High-Priority Cache Block Push Operation ................................4-22
Cache Control Instructions ................................................................................4-22
Data Cache Block Invalidate (
dcbi
) Instruction............................................4-24
Data Cache Block Touch (
dcbt
) Instruction..................................................4-24
Data Cache Block Touch for Store (
dcbtst
) Instruction................................4-24
Data Cache Block Clear to Zero (
dcbz
) Instruction......................................4-24
Data Cache Block Store (
dcbst
) Instruction..................................................4-25
Data Cache Block Flush (
dcbf
) Instruction...................................................4-25
Enforce In-Order Execution of I/O (
eieio
) Instruction..................................4-26
Instruction Cache Block Invalidate (
icbi
) Instruction ...................................4-26
Instruction Synchronize (
isync
) Instruction ..................................................4-26
System Bus Interface and Cache Instructions....................................................4-26
Bus Interface......................................................................................................4-27
MEI State Transactions......................................................................................4-29
Cache Locking...................................................................................................4-31
Cache Locking Terminology .........................................................................4-32
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Freescale Semiconductor, Inc.
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