Contents
Paragraph
Number
Title
Page
Number
xviii
G2 PowerPC Core Reference Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9.1.4
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.2.1
9.3.2.2
9.3.2.2.1
9.3.2.2.2
9.3.2.3
9.3.2.4
9.3.2.5
9.3.2.5.1
9.3.2.6
9.3.3
9.4
9.4.1
9.4.1.1
9.4.2
9.4.3
9.4.4
9.4.4.1
9.4.4.2
9.4.4.3
9.4.5
9.5
9.6
9.6.1
9.6.2
9.6.3
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.8
9.8.1
9.8.2
Direct-Store Accesses......................................................................................9-5
Memory Access Protocol.....................................................................................9-5
Arbitration Signals...........................................................................................9-6
Address Pipelining and Split-Bus Transactions...............................................9-7
Timing Diagram Conventions..........................................................................9-8
Address Bus Tenure.............................................................................................9-9
Address Bus Arbitration ..................................................................................9-9
Address Transfer............................................................................................ 9-11
Address Bus Parity ....................................................................................9-12
Address Transfer Attribute Signals............................................................9-12
Transfer Type (core_tt_in[0:4], core_tt_out[0:4]) Signals ....................9-13
Transfer Size (core_tsiz[0:2]) Signals...................................................9-13
Burst Ordering During Data Transfers ......................................................9-14
Effect of Alignment in Data Transfers (64-Bit Bus) .................................9-14
Effect of Alignment in Data Transfers (32-Bit Bus) .................................9-16
Alignment of External Control Instructions..........................................9-18
Transfer Code (core_tc[0:1]) Signals ........................................................9-19
Address Transfer Termination ......................................................................9-19
Data Bus Tenure.................................................................................................9-21
Data Bus Arbitration......................................................................................9-21
Using the core_dbb_out Signal..................................................................9-22
Data Bus Write Only......................................................................................9-23
Data Transfer .................................................................................................9-23
Data Transfer Termination.............................................................................9-24
Normal Single-Beat Termination...............................................................9-25
Normal Burst Termination.........................................................................9-26
Data Transfer Termination Due to a Bus Error..........................................9-27
Memory Coherency—MEI Protocol .............................................................9-29
Timing Examples...............................................................................................9-31
Optional Bus Configurations.............................................................................9-37
32-Bit Data Bus Mode...................................................................................9-37
No-core_drtry Mode......................................................................................9-39
Reduced-Pinout Mode...................................................................................9-40
Interrupt, Checkstop, and Reset Signals............................................................9-40
External Interrupts .........................................................................................9-41
Checkstops.....................................................................................................9-41
Reset Inputs....................................................................................................9-41
Core Quiesce Control Signals........................................................................9-41
Processor State Signals......................................................................................9-42
Support for the
lwarx/stwcx.
Instruction Pair...............................................9-42
core_tlbisync Input ........................................................................................9-42
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Freescale Semiconductor, Inc.
n
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