Contents
Paragraph
Number
Title
Page
Number
MOTOROLA
Contents
vii
Chapter 2
Register Model
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
Register Set..........................................................................................................2-1
PowerPC Register Set......................................................................................2-1
Implementation-Specific Registers..................................................................2-9
Hardware Implementation Register 0 (HID0)...........................................2-10
Hardware Implementation Register 1 (HID1)...........................................2-14
Hardware Implementation Register 2 (HID2)...........................................2-14
Data and Instruction TLB Miss Address Registers
(DMISS and IMISS)..............................................................................2-16
Data and Instruction TLB Compare Registers
(DCMP and ICMP)................................................................................2-16
Primary and Secondary Hash Address Registers
(HASH1 and HASH2)...........................................................................2-17
Required Physical Address Register (RPA)...............................................2-17
BAT Registers (BAT4–BAT7)—G2_LE Only ..........................................2-18
Critical Interrupt Save/Restore Register 0 (CSRR0)—G2_LE Only........2-19
Critical Interrupt Save/Restore Register 1 (CSRR1)—G2_LE Only........2-19
SPRG4–SPRG7 (G2_LE Only).................................................................2-20
System Version Register (SVR)—G2_LE Only........................................2-20
System Memory Base Address (MBAR)—G2_LE Only..........................2-20
Instruction Address Breakpoint Registers (IABR and IABR2).................2-21
Instruction Address Breakpoint Control Registers (IBCR)—
G2_LE Only ......................................................................................2-21
Data Address Breakpoint Register (DABR and DABR2)—
G2_LE Only ..........................................................................................2-22
Data Address Breakpoint Control Registers (DBCR)—
G2_LE-Only......................................................................................2-24
2.1.2.5
2.1.2.6
2.1.2.7
2.1.2.8
2.1.2.9
2.1.2.10
2.1.2.11
2.1.2.12
2.1.2.13
2.1.2.14
2.1.2.14.1
2.1.2.15
2.1.2.15.1
Chapter 3
Instruction Set Model
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.1.1
Operand Conventions ..........................................................................................3-1
Data Organization in Memory and Memory Operands...................................3-1
Endian Modes and Byte Ordering ...................................................................3-1
Alignment and Misaligned Accesses...............................................................3-2
Floating-Point Execution Model......................................................................3-3
Effect of Operand Placement on Performance ................................................3-4
Instruction Set Summary .....................................................................................3-5
Classes of Instructions.....................................................................................3-6
Definition of Boundedly Undefined............................................................3-6
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