Contents
Paragraph
Number
Title
Page
Number
MOTOROLA
Contents
xv
8.3.2.1.1
8.3.2.1.2
8.3.3
8.3.3.1
8.3.3.1.1
8.3.3.1.2
8.3.3.1.3
8.3.3.1.4
8.3.3.2
8.3.3.2.1
8.3.3.2.2
8.3.3.2.3
8.3.3.3
8.3.3.3.1
8.3.3.3.2
Transfer Start In (core_ts_in).................................................................8-14
Transfer Start Out (core_ts_out)............................................................8-15
Address Transfer Signals...............................................................................8-15
Address Bus ..............................................................................................8-15
Address Bus In (core_a_in[0:31]) .........................................................8-15
Address Bus Out (core_a_out[0:31]).....................................................8-15
Address Bus Output Enable (core_a_oe)—Output ...............................8-16
Address Bus High-Impedance Enable (core_a_tre)—Input..................8-16
Address Bus Parity ....................................................................................8-17
Address Bus Parity In (core_ap_in[0:3])...............................................8-17
Address Bus Parity Input Enable (core_ap_ien)—Output ....................8-17
Address Bus Parity Out (core_ap_out[0:3])..........................................8-17
Address Parity Error (core_ape)—Output.................................................8-18
Address Parity Error Output Enable (core_ape_oe)—Output...............8-18
Address Parity Error High-Impedance Enable (core_ape_tre)—
Input...................................................................................................8-19
Address Transfer Attribute Signals................................................................8-19
Transfer Type.............................................................................................8-19
Transfer Type In (core_tt_in[0:4]).........................................................8-20
Transfer Type Out (core_tt_out[0:4])....................................................8-21
Transfer Size (core_tsiz[0:2])—Output.....................................................8-22
Transfer Burst............................................................................................8-23
Transfer Burst In (core_tbst_in) ............................................................8-23
Transfer Burst Out (core_tbst_out)........................................................8-23
Transfer Code (core_tc[0:1])—Output......................................................8-24
Cache Inhibit (core_ci)—Output...............................................................8-24
Write-Through (core_wt)—Output............................................................8-24
Global Signals............................................................................................8-25
Global In (core_gbl_in).........................................................................8-25
Global Out (core_gbl_out).....................................................................8-25
Cache Set Entry (core_cse[0:1])—Output.................................................8-25
Address Transfer Termination Signals...........................................................8-26
Address Acknowledge (core_aack)—Input...............................................8-26
Address Retry ...........................................................................................8-26
Address Retry In (core_artry_in)...........................................................8-26
Address Retry Out (core_artry_out)......................................................8-27
Address Retry Output Enable (core_artry_oe)—Output.......................8-28
Address Retry High-Impedance Enable (core_artry_tre)—Input .........8-28
Data Bus Arbitration Signals.........................................................................8-29
Data Bus Grant (core_dbg)—Input ...........................................................8-29
Data Bus Write Only (core_dbwo)—Input................................................8-29
8.3.4
8.3.4.1
8.3.4.1.1
8.3.4.1.2
8.3.4.2
8.3.4.3
8.3.4.3.1
8.3.4.3.2
8.3.4.4
8.3.4.5
8.3.4.6
8.3.4.7
8.3.4.7.1
8.3.4.7.2
8.3.4.8
8.3.5
8.3.5.1
8.3.5.2
8.3.5.2.1
8.3.5.2.2
8.3.5.2.3
8.3.5.2.4
8.3.6
8.3.6.1
8.3.6.2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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