Contents
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Title
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G2 PowerPC Core Reference Manual
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MOTOROLA
5.5.1.2
5.5.1.3
5.5.2
5.5.2.1
5.5.2.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.6.1
5.5.6.2
5.5.7
5.5.7.1
5.5.7.2
Soft Reset...................................................................................................5-21
Byte Ordering Considerations for G2_LE Only........................................5-21
Machine Check Exception (0x00200)...........................................................5-22
Machine Check Exception Enabled (MSR[ME] = 1)................................5-23
Checkstop State (MSR[ME] = 0) ..............................................................5-24
DSI Exception (0x00300)..............................................................................5-24
ISI Exception (0x00400)................................................................................5-27
External Interrupt (0x00500).........................................................................5-27
Alignment Exception (0x00600) ...................................................................5-28
Integer Alignment Exceptions...................................................................5-29
Load/Store Multiple Alignment Exceptions..............................................5-30
Program Exception (0x00700).......................................................................5-31
IEEE Floating-Point Exception Program Exceptions................................5-31
Illegal, Reserved, and Unimplemented Instructions
Program Exceptions...............................................................................5-32
Floating-Point Unavailable Exception (0x00800).........................................5-32
Decrementer Exception (0x00900)................................................................5-32
Critical Interrupt Exception (0x00A00)—G2_LE Only................................5-33
System Call Exception (0x00C00) ................................................................5-34
Trace Exception (0x00D00)...........................................................................5-34
Single-Step Instruction Trace Mode..........................................................5-35
Branch Trace Mode ...................................................................................5-36
Instruction TLB Miss Exception (0x01000)..................................................5-36
Data TLB Miss on Load Exception (0x01100)..............................................5-36
Data TLB Miss on Store Exception (0x01200).............................................5-37
Instruction Address Breakpoint Exception (0x01300)..................................5-37
System Management Interrupt (0x01400).....................................................5-39
5.5.8
5.5.9
5.5.10
5.5.11
5.5.12
5.5.12.1
5.5.12.2
5.5.13
5.5.14
5.5.15
5.5.16
5.5.17
Chapter 6
Memory Management
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.6.1
6.1.6.2
6.1.7
6.1.8
MMU Features.....................................................................................................6-2
Memory Addressing ........................................................................................6-3
MMU Organization..........................................................................................6-3
Address Translation Mechanisms....................................................................6-8
Memory Protection Facilities.........................................................................6-10
Page History Information............................................................................... 6-11
General Flow of MMU Address Translation................................................. 6-11
Real Addressing Mode and Block Address Translation Selection............ 6-11
Page Address Translation Selection ..........................................................6-12
MMU Exceptions Summary..........................................................................6-14
MMU Instructions and Register Summary....................................................6-17
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