Contents
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Number
Title
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vi
G2 PowerPC Core Reference Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
1.1.8.1
1.1.8.2
1.1.8.3
1.1.8.4
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.3.1.6
1.3.1.7
1.3.1.7.1
1.3.1.7.2
1.3.2
1.3.2.1
1.3.2.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.4
1.3.4.1
1.3.4.2
1.3.5
1.3.5.1
1.3.5.2
1.3.6
1.3.7
1.3.7.1
1.3.7.2
1.3.8
1.3.8.1
1.3.8.2
1.3.8.3
1.3.8.4
1.4
Power Management...................................................................................1-14
Time Base/Decrementer ............................................................................1-14
IEEE 1149.1 (JTAG)/COP Test Interface..................................................1-15
Clock Multiplier.........................................................................................1-15
PowerPC Architecture Implementation.............................................................1-15
Implementation-Specific Information................................................................1-16
Register Model...............................................................................................1-17
General-Purpose Registers (GPRs)............................................................1-17
Floating-Point Registers (FPRs)................................................................1-17
Condition Register (CR)............................................................................1-19
Floating-Point Status and Control Register (FPSCR) ...............................1-19
Machine State Register (MSR)..................................................................1-19
Segment Registers (SRs) ...........................................................................1-19
Special-Purpose Registers (SPRs).............................................................1-19
User-Level SPRs....................................................................................1-20
Supervisor-Level SPRs..........................................................................1-20
Instruction Set and Addressing Modes..........................................................1-22
PowerPC Instruction Set and Addressing Modes......................................1-22
Implementation-Specific Instruction Set...................................................1-24
Cache Implementation...................................................................................1-24
PowerPC Cache Characteristics ................................................................1-24
Implementation-Specific Cache Implementation......................................1-25
Instruction and Data Cache Way-Locking.................................................1-26
Exception Model............................................................................................1-26
PowerPC Exception Model........................................................................1-26
Implementation-Specific Exception Model...............................................1-28
Memory Management....................................................................................1-31
PowerPC Memory Management................................................................1-31
Implementation-Specific Memory Management.......................................1-31
Instruction Timing .........................................................................................1-32
System Interface ............................................................................................1-34
Memory Accesses......................................................................................1-35
Signals........................................................................................................1-35
Debug Features (G2_LE Only)......................................................................1-37
Instruction Address Breakpoint Registers (IABR and IABR2).................1-37
Data Address Breakpoint Registers (DABR and DABR2) .......................1-38
Breakpoint Signaling.................................................................................1-38
Other Debug Resources.............................................................................1-38
Differences Between the MPC603e and the G2 and G2_LE Cores ..................1-39
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