Contents
Paragraph
Number
Title
Page
Number
xvi
G2 PowerPC Core Reference Manual
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MOTOROLA
8.3.6.3
8.3.6.3.1
8.3.6.3.2
8.3.6.3.3
8.3.6.3.4
8.3.7
8.3.7.1
8.3.7.1.1
8.3.7.1.2
8.3.7.1.3
8.3.7.1.4
8.3.7.1.5
8.3.7.2
8.3.7.2.1
8.3.7.2.2
8.3.7.2.3
8.3.7.3
8.3.7.3.1
8.3.7.3.2
8.3.7.4
8.3.8
8.3.8.1
8.3.8.2
8.3.8.3
8.3.9
8.3.9.1
8.3.9.2
8.3.9.3
8.3.9.4
8.3.9.5
8.3.9.5.1
8.3.9.5.2
8.3.9.5.3
8.3.9.5.4
8.3.10
8.3.10.1
8.3.10.2
8.3.10.3
8.3.10.3.1
8.3.10.3.2
8.3.10.3.3
Data Bus Busy ..........................................................................................8-30
Data Bus Busy In (core_dbb_in)...........................................................8-30
Data Bus Busy Out (core_dbb_out).......................................................8-30
Data Bus Busy Output Enable (core_dbb_oe)—Output........................8-31
Data Bus Busy High-Impedance Enable (core_dbb_tre)—Input..........8-31
Data Transfer Signals.....................................................................................8-31
Data Bus ....................................................................................................8-32
Data Bus In (core_dh_in[0:31], core_dl_in[0:31])................................8-32
Data Bus Input Enable (core_dh_ien, core_dl_ien)—Output ...............8-32
Data Bus Out (core_dh_out[0:31], core_dl_out[0:31])—Output..........8-33
Data Bus Output Enable (core_d_oe)—Output.....................................8-33
Data Bus High-Impedance Enable (core_d_tre)—Input.......................8-34
Data Bus Parity (DP[0:7]) .........................................................................8-34
Data Bus Parity In (core_dp_in[0:7])....................................................8-34
Data Bus Parity Input Enable (core_dp_ien)—Output..........................8-35
Data Bus Parity Out (core_dp_out[0:7]) ...............................................8-35
Data Parity Error (core_dpe)—Output ......................................................8-35
Data Parity Error Output Enable (core_dpe_oe)—Output....................8-36
Data Parity Error High-Impedance Enable (core_dpe_tre)—Input.......8-36
Data Bus Disable (core_dbdis)—Input......................................................8-36
Data Transfer Termination Signals................................................................8-37
Transfer Acknowledge (core_ta)—Input...................................................8-37
Data Retry (core_drtry)—Input.................................................................8-38
Transfer Error Acknowledge (core_tea)—Input........................................8-38
Interrupt and Checkstop Signals....................................................................8-39
External Interrupt (core_int)—Input..........................................................8-39
Critical Interrupt (core_cint)—Input: G2_LE Core-Only .........................8-39
System Management Interrupt (core_smi)—Input....................................8-40
Machine Check Interrupt (core_mcp)—Input...........................................8-40
Checkstop Signals......................................................................................8-41
Checkstop Input (core_ckstp_in)...........................................................8-41
Checkstop Output (core_ckstp_out)......................................................8-41
Checkstop Output Enable (core_ckstp_oe)—Output............................8-42
Checkstop High-Impedance Enable (core_ckstp_tre)—Input...............8-42
Reset Signals..................................................................................................8-42
Hard Reset (core_hreset)—Input...............................................................8-42
Soft Reset (core_sreset)—Input.................................................................8-43
Reset Configuration Signals......................................................................8-43
32-Bit Mode (core_32bitmode)—Input.................................................8-43
Reduced Pinout Mode (core_redpinmode)—Input ...............................8-44
MSR IP Bit Set Mode (core_msrip)—Input..........................................8-44
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