Contents
Paragraph
Number
Title
Page
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xiv
G2 PowerPC Core Reference Manual
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MOTOROLA
7.3.3.3
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.1.2.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.5.1
7.5.2
7.5.3
7.6
7.6.1
7.6.1.1
7.6.1.2
7.6.1.3
7.7
Execution Unit Considerations..................................................................7-16
Execution Unit Timings.....................................................................................7-16
Branch Processing Unit Execution Timing....................................................7-16
Branch Folding ..........................................................................................7-17
Static Branch Prediction ............................................................................7-18
Predicted Branch Timing Examples......................................................7-19
Integer Unit Execution Timing......................................................................7-20
Floating-Point Unit Execution Timing ..........................................................7-21
Load/Store Unit Execution Timing................................................................7-21
System Register Unit Execution Timing .......................................................7-21
Memory Performance Considerations ...............................................................7-22
Copy-Back Mode...........................................................................................7-22
Write-Through Mode.....................................................................................7-23
Cache-Inhibited Accesses..............................................................................7-23
Instruction Scheduling Guidelines.....................................................................7-23
Branch, Dispatch, and Completion Unit Resource Requirements.................7-24
Branch Resolution Resource Requirements ..............................................7-24
Dispatch Unit Resource Requirements......................................................7-25
Completion Unit Resource Requirements.................................................7-25
Instruction Latency Summary............................................................................7-26
Chapter 8
Signal Descriptions
8.1
8.2
8.2.1
8.2.2
8.2.2.1
8.2.2.2
8.2.3
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.1.3
8.3.1.3.1
8.3.1.3.2
8.3.1.3.3
8.3.1.3.4
8.3.2
8.3.2.1
Signal Groupings .................................................................................................8-1
Signal Configurations..........................................................................................8-3
Functional Groupings ......................................................................................8-3
Input/Output Enable and High-Impedance Control Signals............................8-3
Unidirectional/Bidirectional Signals ...........................................................8-5
Logic Gate Equivalent and Bidirectional Signals........................................8-5
Signal Summary...............................................................................................8-6
Signal Descriptions............................................................................................8-10
Address Bus Arbitration Signals.................................................................... 8-11
Bus Request (core_br)—Output................................................................ 8-11
Bus Grant (core_bg)—Input...................................................................... 8-11
Address Bus Busy .....................................................................................8-12
Address Bus Busy In (core_abb_in)......................................................8-12
Address Bus Busy Out (core_abb_out).................................................8-13
Address Bus Busy Output Enable (core_abb_oe)—Output..................8-13
Address Bus Busy High-Impedance Enable (core_abb_tre)—Input.....8-14
Address Transfer Start Signals.......................................................................8-14
Transfer Start .............................................................................................8-14
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