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参数资料
| 型号： | HFA3824A |
| 厂商： | Intersil Corporation |
| 元件分类： | 基带处理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | 直接序列扩频基带处理器 |
| 文件页数： | 16/40页 |
| 文件大小： | 271K |
| 代理商： | HFA3824A |
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2-114
Mode 2 -
In this mode the preamble is programmable up to 256
bits (all 1’s) and the SFD, Length Field, and CCITT - CRC 16
fields are used for the header. The data that follows the header
can be either DBPSK or DQPSK. The receiver and transmitter
must be programmed to the proper modulation type.
Mode 3 -
In this mode the preamble is programmable up to
256 bits (all 1’s). The header in this mode is using all available
fields. In mode 3 the signal field defines the modulation type of
the data packet (DBPSK or DQPSK) so the receiver does not
need to be preprogrammed to anticipate one or the other. In
this mode the device checks the Signal field for the data
packet modulation and it switches to DQPSK if it is defined as
such in the signal field. Note that the preamble and header
are always DBPSK the modulation definition applies only for
the data packet. This mode is called the full protocol mode in
this document.
Figure 10 summarizes the four preamble/head or modes. In the
case that the device is configured to accept the preamble and
header from an external source it still needs to be configured in
one of the four modes (0:3). Even though the HFA3824A trans-
mitter does not generate the preamble and header information
the receiver needs to know the mode in use so it can proceed
with the proper protocol and demodulation decisions.
The following Configuration Registers (CR)are used to program
the preamble/header functions, more programming details
about these registers can be found in the Control Registers
section of this document:
CR 0 -
Defines one of the four modes (bits 4, 3) for the TX.
Defines whether the SFD timer is active (bit 2). Defines whether
the receiver should stop demodulating after the number of sym-
bols indicated in the Length field has been met.
CR 2 -
Defines to the receiver one of the four protocol modes
(bits 1, 0). Indicates whether any detected CCITT - CRC 16
errors need to reset the receiver (return to acquisition) or to
ignore them and continue with demodulation (bit 5). Specifies a
128-bit preamble or an 80-bit preamble (bit 2).
CR 3 -
Defines internal or external preamble generation (bit 2).
Indicates to the receiver the data packet modulation (bit 0), note
that in mode 3 the contents of this register are overwritten by
the information in the received signal field of the header. CR 3
specifies the data modulation type used to the transmitter (bit
1). Bit 1 defines the contents of the signaling field in the header
to indicate either DBPSK or DQPSK modulation.
CR 41 -
Defines the length of time that the demodulator
searches for the SFD before returning to acquisition.
CR 42 -
The contents of this register indicate that the transmit-
ted data is DBPSK. If CR 4-bit 1 is set to indicate DBPSK mod-
ulation then the contents of this register are transmitted in the
signal field of the header.
CR 43 -
The contents of this register indicates that the transmit-
ted data is DQPSK. If CR 4-bit 1 is set to indicate DQPSK mod-
ulation then the contents of this register are transmitted in the
signal field of the header.
CR 44, 45, 46, 47, 48 -
Status, read only, registers that indicate
the service field, data length field and CCITT - CRC 16 field val-
ues of the received header.
CR 49, 50 -
Defines the transmit SFD field value of the header.
The receiver will always search to detect this value before it
declares a valid data packet.
CR 51 -
Defines the contents of the transmit service field.
CR 52, 53 -
Defines the value of the transmit data length
field. This value includes all symbols following the last
header field symbol.
CR 54,55 -
Status, read only, registers indicating the calculated
CCITT - CRC 16 value of the most recently transmitted header.
CR 56 -
Defines the number of preamble synchronization bits
that need to be transmitted when the preamble is internally
generated. These symbols are used by the receiver for initial
PN acquisition and they are followed by the header fields.
The full protocol requires a setting of 128d = 80h. For other
applications, in general increasing the preamble length will
improve low signal to noise acquisition performance at the cost
of greater link overhead. For dual receive antenna operation,
the minimum suggested value is 128d = 80h. For single receive
antenna operation, the minimum suggested value is 80d = 50h.
These suggested values include a 2 symbol TX power amplifier
ramp up. If an AGC is used, its worst case settling time in sym-
bols should be added to these values.
PN Generator Description
The spread function for this radio uses short sequences. The
same sequence is applied to every symbol. All transmitted
symbols, preamble/header and data are always spread by the
PN sequence at the chip rate. The PN sequence sets the Pro-
cessing Gain (PG) of the Direct Sequence receiver. The
HFA3824A can be programmed to utilize 11, 13, 15 and 16 bit
HEADER
COUNT
CR #0 BITS
BIT 4
BIT 3
N (Preamble) +
16 (Header) Bits
0
0
N (Preamble) +
32 (Header) Bits
0
1
N (Preamble) +
48 (Header) Bits
1
0
N (Preamble) +
64 (Header) Bits
1
1
Preamble (SYNC)
N Bits Up to 256)
Preamble (SYNC)
N Bits Up to 256)
Preamble (SYNC)
N Bits Up to 256)
Preamble (SYNC)
N Bits Up to 256)
SFD
16 Bits
SFD
16 Bits
SFD
16 Bits
SFD
16 Bits
CRC16
16 Bits
Length Field
16 Bits
Signal Field
8 Bits
Service Field
8 Bits
CRC16
16 Bits
Length Field
16 Bits
CRC16
16 Bits
HEADER
PREAMBLE
FIGURE 10. PREAMBLE/HEADER MODES
HFA3824A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3824AIV | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824AIV96 | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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