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参数资料
| 型号： | HFA3824A |
| 厂商： | Intersil Corporation |
| 元件分类： | 基带处理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | 直接序列扩频基带处理器 |
| 文件页数： | 21/40页 |
| 文件大小： | 271K |
| 代理商： | HFA3824A |
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2-119
PN Correlator Description
The PN correlator is designed to handle BPSK spreading
with carrier offsets up to
±
50ppm and 11,13,15 or 16 chips
per symbol. Since the spreading is BPSK, the correlator is
implemented with two real correlators, one for the I and one
for the Q channel. The same sequence is always used for
both I an Q correlators. The TX sequence can be pro-
grammed as a different sequence from the RX sequence.
This allows a full duplex link with different spreading parame-
ters for each direction.
The correlators are time invariant matched filters otherwise
known as parallel correlators. They use two samples per
chip. The correlator despreads the samples from the chip
rate back to the original data rate giving 10.4dB processing
gain for 11 chips per bit. While despreading the desired sig-
nal, the correlator spreads the energy of any non correlating
interfering signal.
Based on the fact that correlator output pulse is used for bit
timing, the HFA3824A can not be used for any non spread
applications.
In programming the correlator functions, there are two sets
of configuration registers that are used to program the
spread sequences of the transmitter and the receiver. They
are CR 13 and 14 for transmitter and CR 20 and 21 for the
receiver. In addition, CR2 and CR3 define the sequence
length or chips per symbol for the receiver and transmitter
respectively. These are carried in bits 6 and 7 of CR2 and
bits 5 and 6 of CR3. More programming details are given in
the Control Registers section of this document.
Data Demodulation and Tracking
Description
The signal is demodulated from the correlation peaks
tracked by the symbol timing loop (bit sync). The frequency
and phase of the signal is corrected from the NCO that is
driven by the phase locked loop. Demodulation of the DPSK
data in the early stages of acquisition is done by delay and
subtraction of the phase samples. Once phase locked loop
tracking of the carrier is established, coherent demodulation
is enabled for better performance. Averaging the phase
errors over 16 symbols gives the necessary frequency infor-
mation for proper NCO operation. The signal quality is taken
as the variance in this estimate.
There are two signal quality measurements that are per-
formed in real time by the device and they set the demodula-
tor performance. The thresholds for these signal quality
measurements are user programmable. The same two sig-
nal quality measures, phase error and bit sync amplitude,
that are used in acquisition are also used for the data drop
lock decision. The data thresholds, though, are programmed
independently from the acquisition thresholds. If the radio
uses the network processor to determine when to drop the
signal, the thresholds for these decisions should be set to
their limits allowing data demodulation even with poor signal
reception. Under this configuration the HFA3824A data mon-
itor mechanism is essentially bypassed and data monitoring
becomes the responsibility of the network processor.
These signal quality measurements are integrated over 128
symbols as opposed to 16 symbol intervals for acquisition,
so the minimum time to drop lock based with these thresh-
olds is 128 symbols or 128ms at 1 MSPS. Note that other
than the data thresholds, non-detection of the SFD can
cause the HFA3824A to drop lock and return its acquisition
mode.
Configuration Register 41 sets the search timer for the SFD.
This register sets this time-out length in symbols for the
receiver. If the time out is reached, and no SFD is found, the
receiver resets to the acquisition mode. The suggested value
is preamble symbols + 16 symbols. If several transmit pream-
ble lengths are used by various transmitters in a network, the
longest value should be used for the receiver settings.
Procedure to Set Signal Quality Registers
CR 26, 27, 34, AND 35 (RX_SQX_IN_DATA) are pro-
grammed to hold the threshold values that are used to drop
lock if the signal quality drops below their values. These can
be set to their limit values if the external network processor
is used for drop lock decisions instead of the HFA3824A
demodulator. The signal quality values are averaged over
128 symbols and if the bit sync amplitude value drops below
its threshold or the phase noise rises over its threshold, the
T0 + 1
μ
s
CORRELATOR
OUTPUT
REPEATS
CORRELATION
PEAK
T0 + 2
μ
s
T0
CORRELATOR OUTPUT IS
THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE
RECEIVED SIGNAL
SAMPLES
AT 2X CHIP
RATE
EARLY
ON-TIME
LATE
CORRELATION TIME
FIGURE 16. CORRELATION PROCESS
HFA3824A
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| HFA3842BIN | PCMCIA/USB Wireless LAN Medium Access Controller |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3824AIV | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824AIV96 | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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