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参数资料
| 型号： | HFA3824A |
| 厂商： | Intersil Corporation |
| 元件分类： | 基带处理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | 直接序列扩频基带处理器 |
| 文件页数： | 23/40页 |
| 文件大小： | 271K |
| 代理商： | HFA3824A |
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2-121
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data
clock offsets of up to
±
25ppm for each end of the link (TX
and RX). This effects both the acquisition and the tracking
performance of the demodulator. The budget for clock offset
error is 0.75dB at
±
50ppm as shown in Figure 18.
Carrier Offset Frequency Performance
The correlators in the baseband processor are time invariant
matched filter correlators otherwise known as parallel correla-
tors. They use two samples per chip and are tapped at every
other shift register stage. Their performance with carrier fre-
quency offsets is determined by the phase roll rate due to the
offset. For an offset of +50ppm (combined for both TX and RX)
will cause the carrier to phase roll 22.5 degrees over the length
of the correlator. This causes a loss of 0.22dB in correlation
magnitude which translates directly to Eb/N0 performance loss.
In the PRISM chip design, the correlator is not included in the
carrier phase locked loop correction, so this loss occurs for both
acquisition and data. Figure 19 shows the loss versus carrier
offset taken out to +350kHz (120kHz is 50ppm at 2.4GHz).
Offset data taken with QPSK data.
I/Q Amplitude Imbalance
Imbalances in the signal cause differing effects depending
on where they occur. In a system using a limiter, if the imbal-
ances are in the transmitter, that is, before the limiter, ampli-
tude imbalances translate into phase imbalances between
the I and Q symbols. If they occur in the receiver after the
limiter, they are not converted to phase imbalances in the
symbols, but into vector phase imbalances on the composite
signal plus noise. The following curve shows data taken with
amplitude imbalances in the transmitter. Starting at the bal-
anced condition, I = 100% of Q, the bit error rate degrades
by two orders of magnitude for a 3dB drop in I (70%).
A Default Register Configuration
The registers in the HFA3824A are addressed with 14-bit
numbers where the lower 2 bits of a 16-bit hexadecimal
address are left as unused. This results in the addresses
being in increments of 4 as shown in the table below. Table 10
shows the register values for a default Full Protocol configura-
tion (Mode 3) with a single antenna. The data is transmitted
as DQPSK. This is a recommended configuration for initial
test and verification of the device and /or the radio design. The
user can later modify the CR contents to reflect the system
and the required performance of each specific application.
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1
1
1
1
1
1
9
8
Eb/N0 IN dB
B
THEORY (DBPSK)
DBPSK
DQPSK
FIGURE 17. BER vs EB/N0 PERFORMANCE
1E-5
1E-4
1E-3
-100
-60
-20
20
60
100
OFFSET IN ppm
B
FIGURE 18. BER vs CLOCK OFFSET
1E-6
1E-5
1E-4
1E-3
-
-
-
-
5
1
2
3
FREQUENCY OFFSET (kHz)
B
FIGURE 19. BER vs CARRIER OFFSET
1E-05
1E-04
1E-03
1E-02
1E-01
1
9
8
8
7
7
PERCENT AMPLITUDE BALANCE
8
B
9
6
FIGURE 20. I/Q IMBALANCE EFFECTS
HFA3824A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3824AIV | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824AIV96 | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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