参数资料
型号: HFA3824A
厂商: Intersil Corporation
元件分类: 基带处理器
英文描述: Direct Sequence Spread Spectrum Baseband Processor
中文描述: 直接序列扩频基带处理器
文件页数: 34/40页
文件大小: 271K
代理商: HFA3824A
2-132
CONFIGURATION REGISTER 45 ADDRESS (B4h) RX DATA LENGTH (HIGH)
Bits 0 - 7
This register contains the detected higher byte (bits 8-15) of the received Length Field contained in the Header. This byte
combined with the lower byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER 46 ADDRESS (B8h) RX DATA LENGTH (LOW)
Bits 0 - 7
This register contains the detected lower byte of the received Length Field contained in the Header. This byte combined with
the upper byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER 47 ADDRESS (BCh) RX CRC16 (HIGH)
Bits 0 - 7
This register contains the upper byte bits (8 -15) of the received CRC16 field Header. This register combined with the lower
byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by configuring the
header control bits at configuration register 2.
CONFIGURATION REGISTER 48 ADDRESS (C0h) RX CRC16 (LOW)
Bits 0 - 7
This register contains the lower byte bits (0-7) of the received CRC16 field Header. This register combined with the upper
byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by configuring the
header control bits at configuration register 2.
MSB
LSB
RX_CRC16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_CRC16(HIGH)
7 6 5 4 3
2 1 0
RX_CRC16(LOW)
7 6 5 4 3 2 1 0
NOTE: The receive CRC16 Field protects the following fields depending
upon the mode selection, as defined in configuration register 2.
Mode 0 CRC16 not used
Mode 1 CRC16 protects SFD
Mode 2 CRC16 protects SFD, and Length Field
Mode 3 CRC16 protects Signalling Field, Service Field, and Length Field
CONFIGURATION REGISTER 49 ADDRESS (C4h) SFD (HIGH)
Bits 0 - 7
This 8-bit register contains the upper byte bits (8-15) of the SFD used for both the Transmit and Receive header. This register
combined with the lower byte represents the 16-bit value for the SFD field.
CONFIGURATION REGISTER 50 ADDRESS (C8h) SFD (LOW)
Bits 0 - 7
This 8-bit register contains the upper byte bits (0-7) of the SFD used for both the Transmit and Receive header. This register
combined with the lower byte represents the 16-bit value for the SFD field.
CONFIGURATION REGISTER 51 ADDRESS (CCh) TX SERVICE FIELD
Bits 0 - 7
This 8-bit register is programmed with the 8-bit value of the Service Field to be transmitted in a Header. This field is reserved
for future use and should be always a 00h.
CONFIGURATION REGISTER 52 ADDRESS (D0h) TX DATA LENGTH FIELD (HIGH)
Bits 0 - 7
This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte com-
bined with the lower byte indicates the number of bits to be transmitted in the data packet.
CONFIGURATION REGISTER 53 ADDRESS (D4h) TX DATA LENGTH FIELD (LOW)
Bits 0 - 7
This 8-bit register contains the lower byte bits (0-7) of the transmit Length Field described in the Header. This byte combined
with the higher byte indicates the number of bits to be transmitted in the data packet, including the MAC payload header.
CONFIGURATION REGISTER 54 ADDRESS (D8h) TX CRC16 READ (HIGH)
Bits 0 - 7
This 8-bit register contains the upper byte (bits 8-15) of the transmitted CRC16 Field for the Header. This register combined
with the lower byte represents a 16-bit CRC16 value calculated by the HFA3824A to protect the transmitted header. The
fields protected are selected by configuring the header mode control bits at register address 02.
HFA3824A
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