参数资料
型号: HIP2100EVAL2
厂商: Intersil
文件页数: 10/12页
文件大小: 0K
描述: EVAL BOARD 48VDC-5UDC CONVERTER
标准包装: 1
主要目的: 电源管理,半 H 桥驱动器(外部 FET)
已用 IC / 零件: HIP2100
已供物品:
HIP2100
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
A
A1
A2
A3
b
D
D1
D2
E
E1
E2
e
k
L
L1
N
Nd
Ne
P
θ
MIN
0.80
-
-
0.28
2.55
2.55
0.25
0.35
-
4
-
-
NOMINAL
0.90
-
-
0.20 REF
0.33
5.00 BSC
4.75 BSC
2.70
5.00 BSC
4.75 BSC
2.70
0.80 BSC
-
0.60
-
16
4
4
-
-
MAX
1.00
0.05
1.00
0.40
2.85
2.85
-
0.75
0.15
0.60
12
NOTES
-
-
9
9
5, 8
-
9
7, 8
-
9
7, 8
-
-
8
10
2
3
3
9
9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
10
FN4022.14
相关PDF资料
PDF描述
HIP2100EVAL EVAL BOARD MINI HALF BRIDGE
HIP4080AEVAL EVALUATION BOARD HIP4080/4081
HIP4082EVAL EVAL BOARD FET DRIVER HIP4082
HIP4086EVAL EVALUATION BOARD GP HIP4086
HIP6004EVAL1 EVALUATION BOARD HIP6004
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