参数资料
| 型号： | HW-USB-II-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 19/35页 |
| 文件大小： | 0K |
| 描述： | PLATFORM CABLE USB II |
| 产品培训模块： | Extended Spartan 3A FPGA Family S6 Family Overview |
| 标准包装： | 1 |
| 附件类型： | USB 平台线缆 |
| 适用于相关产品： | Xilinx FPGA、CPLDS、平台闪存 PROM、XC18V00 PROM、系统 ACE MPM |
| 产品目录页面： | 600 (CN2011-ZH PDF) |
| 其它名称： | 122-1572 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
Platform Cable USB II
For a complete description on using Platform Cable USB II for indirect programming of third-BPI PROMs and for a complete
list of supported BPI PROMs, refer to XAPP973 , Indirect Programming of BPI PROMs with Virtex-5 FPGAs .
Target Interface Reference Voltage and Signals
Target Reference Voltage Sensing (VREF)
Platform Cable USB II incorporates an over-voltage clamp on the V REF pin of the 2-mm ribbon cable connector. The
clamped voltage (V REF_CLAMP ) supplies high-slew-rate buffers that drive each of the output signals (see Output Driver
Structure ). V REF must be a regulated voltage.
Note: Do not insert a current-limiting resistor in the target system between the V REF supply and pin 2 on the 2-mm connector.
When Platform Cable USB II is idle, a nominal amount of current is drawn from the target system V REF . Figure 19 shows the
V REF current as a function of V REF voltage.
No damage to Platform Cable USB II occurs if the A–B cable is unplugged from the host while the ribbon cable or flying leads
are attached to a powered target system. Similarly, no damage to target systems occurs if Platform Cable USB II is powered
and attached to the target system while the target system power is off.
Bidirectional Signal Pins
Platform Cable USB II provides five bidirectional signal pins: TDI_DIN_MOSI, TDO_DONE_MISO, TCK_CCLK_SCK,
TMS_PROG_SS and HALT_INT_WP. Each pin incorporates the same I/O structure. The state of each pin (reading or
writing) is determined by the current mode of the cable (JTAG, SPI or Slave Serial).
Output Driver Structure
Each output signal is routed through a NC7SZ126 ultra high-speed CMOS buffer ( Figure 20, page 20 ). Series-damping
resistors (30.1 Ω ) reduce reflections. Weak pull-up resistors (20 k Ω ) terminating at V REF_CLAMP maintain a defined logic level
when the buffers are set to high-Z. Schottky diodes provide the output buffers with undershoot protection.
The FPGA sets the output buffers to high-Z when V REF drops below 1.30 V. In addition, an over-voltage Zener on V REF
clamps V REF_CLAMP to approximately 3.9V.
Note: The output drivers are enabled only during cable operations; otherwise, they are set to high-Z between operations.
Xilinx design tools actively drive the outputs to logic 1 before setting the respective buffer to high-Z, avoiding the possibility
of a slow rise-time transition caused by a charge path through the pull-up resistor into parasitic capacitance on the target
system.
DS593 (v1.2.1) March 17, 2011
19
相关PDF资料 |
PDF描述 |
|---|---|
| HW-USBN-2A | ACCY USB DOWNLOAD CABLE STD SPD |
| HW-V4-ML401-USA | EVALUATION PLATFORM VIRTEX-4 |
| HW-V4-ML423-UNI-G | EVALUATION PLATFORM VIRTEX-4 |
| HW-V4SX35-VIDEO-SK-UK | VIRTEX-4 VIDEO STARTER KIT |
| HW-V5-ML521-UNI-G | EVALUATION PLATFORM VIRTEX-5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HW-USBN-2A | 功能描述:程序设计器配件 ispDOWNLOAD Cable RoHS:否 制造商:Lattice 产品:ispDOWNLOAD Cables 用于:In-system Programming |
| HW-USBN-2B | 功能描述:Lattice Programmable Products ispDOWNLOAD? In-System Programmer 制造商:lattice semiconductor corporation 系列:ispDOWNLOAD? 零件状态:有效 类型:系统内编程器 配套使用产品/相关产品:Lattice 可编程产品 内容:编程器 标准包装:1 |
| HW-UW 30 | 制造商:OK International (OKI) / Metcal 功能描述:WRAPPING AND UNWRAPPING TOOL HAND 制造商:OK International (OKI) / Metcal 功能描述:WRAPPING AND UNWRAPPING TOOL, HAND |
| HW-UW-18-19 | 功能描述:手工工具 WRAP-UNWRAP TOOL, 18-19 AWG RoHS:否 制造商:Molex 产品:Extraction Tools 类型: 描述/功能:Extraction tool |
| HW-UW18-19 | 制造商:Jonard Industries 功能描述:WRAP-UNWRAP TOOL, 18-19 AWG |
发布紧急采购，3分钟左右您将得到回复。