参数资料
型号: HW-USB-II-G
厂商: Xilinx Inc
文件页数: 8/35页
文件大小: 0K
描述: PLATFORM CABLE USB II
产品培训模块: Extended Spartan 3A FPGA Family
S6 Family Overview
标准包装: 1
附件类型: USB 平台线缆
适用于相关产品: Xilinx FPGA、CPLDS、平台闪存 PROM、XC18V00 PROM、系统 ACE MPM
产品目录页面: 600 (CN2011-ZH PDF)
其它名称: 122-1572
Platform Cable USB II
iMPACT 7.1i (and later) provides a feature wherein the BSDL file of each device in a target JTAG chain is scanned to
determine the maximum Boundary-Scan clock (JTAG TCK) frequency. iMPACT 7.1i (and later) automatically restricts the
available TCK_CCLK_SCK selections to frequencies less than or equal to the slowest device in the chain. By default,
iMPACT 7.1i (or later) selects either 6 MHz or the highest common frequency when any device in the JTAG chain is not
capable of 6 MHz operation. Table 3 shows the maximum supported JTAG TCK frequency for a variety of Xilinx devices. See
the device data sheet or BSDL file for maximum JTAG TCK specifications.
Note: Certain Xilinx design tools and iMPACT versions earlier than 7.1i do not restrict the TCK_CCLK_SCK selections in JTAG mode.
Accordingly, users should take care to select a TCK_CCLK_SCK frequency matching the JTAG TCK specifications for the slowest device
in the target chain.
In Slave Serial or Direct SPI Configuration mode, the TCK_CCLK_SCK speed can be set to any one of the available
selections. By default, the TCK_CCLK_SCK speed is set to 6 MHz. Users should take care to select a TCK_CCLK_SCK
frequency matching the Slave Serial clock (CCLK or SPI clock) specification of the target device.
Table 3: Maximum JTAG Clock Frequencies
Device Family
XC9500/XL/XV
XPLA3
CoolRunner-II
XC18V00
XCF00S/XCF00P
Virtex
Virtex-II
Virtex-II Pro
Virtex-4
Virtex-5
Spartan
Spartan-II
Spartan-3
Spartan-3A
Spartan-3AN
(50, 200 and 400 densities)
Spartan-3AN
(700 and 1400 densities)
Spartan-3E
DS593 (v1.2.1) March 17, 2011
Maximum JTAG Clock
Frequency (MHz)
10
10
33
10
15
33
33
33
33
33
5
33
33
33
33
20
30
8
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HW-USBN-2A ACCY USB DOWNLOAD CABLE STD SPD
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