参数资料
| 型号： | HW-USB-II-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 23/35页 |
| 文件大小： | 0K |
| 描述： | PLATFORM CABLE USB II |
| 产品培训模块： | Extended Spartan 3A FPGA Family S6 Family Overview |
| 标准包装： | 1 |
| 附件类型： | USB 平台线缆 |
| 适用于相关产品： | Xilinx FPGA、CPLDS、平台闪存 PROM、XC18V00 PROM、系统 ACE MPM |
| 产品目录页面： | 600 (CN2011-ZH PDF) |
| 其它名称： | 122-1572 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
Platform Cable USB II
X-Ref Target - Figure 24
DS593_24_021408
Figure 24: Enabling the HALT Signal in iMPACT (9.2i)
Timing Specifications
For JTAG, SPI, and Slave Serial configuration modes, the TDI_DIN_MOSI and TMS_PROG_SS outputs change on falling
edges of TCK_CCLK_SCK ( Figure 25 ). Target devices sample TDI_DIN_MOSI and TMS_PROG_SS on rising edges of
TCK_CCLK_SCK. The minimum setup time T TSU(MIN) for target device sampling of TDI_DIN_MOSI or TMS_PROG_SS is:
T TSU(MIN)
= T CLK/2 – T CPD(MAX)
= 20.8 ns – 16.0 ns
= 4.8 ns
where:
T CLK/2 = TCK_CCLK_SCK low time at 24 MHz,
T CPD(MAX) = Maximum TDI_DIN_MOSI or TMS_PROG_SS propagation delay relative to TCK_CCLK_SCK inherent in
the output stage of the cable.
Reducing the TCK_CCLK_SCK frequency increases the data setup time at the target.
Note: Timing specifications apply when V REF = 3.3V. Operations at 24 MHz might not be possible when using a V REF below 3.3V due to
the increased propagation delay through the output buffer stage of the cable.
TDO/MISO Timing Considerations
Designers of target systems must take care to observe specific timing requirements for TDO (JTAG chains) or MISO
(dedicated SPI in-system programming) when incorporating the 2-mm IDC connector. In particular, if an open-drain or open-
collector buffer is inserted between TDO (MISO) and the cable, the value of the pull-up resistor at the output of such buffers
must be relatively small (for example, less than 330 Ω ) to avoid delays associated with parasitic capacitance.
Figure 26, page 25 and Figure 27, page 26 show the timing relationship between TCK and TDO. The signal TDO_SMPL is
an internal logic signal not available at the target interface, but is shown to highlight the location of the TDO sampling point.
In Figure 26 , the negative TCK transition at G1 causes the last device in the target system JTAG chain to drive TDO, which
propagates to the cable at G2. The time from G1 to G2 is the sum of the propagation delays in the driver stage of the target
device and the receiver stage of the cable (37 ns in this example).
In Figure 27 , the cursors show the total setup time (42 ns) before TDO is sampled by the cable. Figure 28, page 27 is an
analog representation of the logical condition shown in Figure 26 and Figure 27 captured at the target system.
DS593 (v1.2.1) March 17, 2011
23
相关PDF资料 |
PDF描述 |
|---|---|
| HW-USBN-2A | ACCY USB DOWNLOAD CABLE STD SPD |
| HW-V4-ML401-USA | EVALUATION PLATFORM VIRTEX-4 |
| HW-V4-ML423-UNI-G | EVALUATION PLATFORM VIRTEX-4 |
| HW-V4SX35-VIDEO-SK-UK | VIRTEX-4 VIDEO STARTER KIT |
| HW-V5-ML521-UNI-G | EVALUATION PLATFORM VIRTEX-5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HW-USBN-2A | 功能描述:程序设计器配件 ispDOWNLOAD Cable RoHS:否 制造商:Lattice 产品:ispDOWNLOAD Cables 用于:In-system Programming |
| HW-USBN-2B | 功能描述:Lattice Programmable Products ispDOWNLOAD? In-System Programmer 制造商:lattice semiconductor corporation 系列:ispDOWNLOAD? 零件状态:有效 类型:系统内编程器 配套使用产品/相关产品:Lattice 可编程产品 内容:编程器 标准包装:1 |
| HW-UW 30 | 制造商:OK International (OKI) / Metcal 功能描述:WRAPPING AND UNWRAPPING TOOL HAND 制造商:OK International (OKI) / Metcal 功能描述:WRAPPING AND UNWRAPPING TOOL, HAND |
| HW-UW-18-19 | 功能描述:手工工具 WRAP-UNWRAP TOOL, 18-19 AWG RoHS:否 制造商:Molex 产品:Extraction Tools 类型: 描述/功能:Extraction tool |
| HW-UW18-19 | 制造商:Jonard Industries 功能描述:WRAP-UNWRAP TOOL, 18-19 AWG |
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