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参数资料
型号： HW-V5-ML550-UNI-G
厂商： Xilinx Inc
文件页数： 33/88页
文件大小： 0K
描述： EVALUATION PLATFORM VIRTEX-5
产品变化通告： Adapter Replacement 23/May/2008
Development Systems Discontinuation 26/Apr/2011
标准包装： 1
系列： Virtex®-5 LXT
类型： FPGA
适用于相关产品： XC5VLX50T-FFG1136
所含物品： 开发平台，电源，回送板，小型闪存卡，软件和文档
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R
Power Monitor Connector
voltage taps on each resistor are wired to the P72 Power Monitor connector. Figure 3-10
shows a typical current sense resistor topology.
R384
RES_CUR_SENSE_SMT
V CC2V5 V AUX
V CC2V5 V AUX SR1
1
R1
R2
4
1
R220 2
V CC2V5 V AUX MON
SMV_R4723
1.0K
R010
V CC2V5 V AUX S-
V CC2V5 V AUX S+
ug202_3_10_032607
Figure 3-10:
Typical Current Sense Resistor Topology
In this case, V CC2V5_VAUX_SR1 is the 2.5V V AUX voltage regulator output trace. It is
connected to the “input” side of a 10 m Ω 1% Kelvin resistor. The “output” side of the
resistor feeds the 2.5V V AUX power plane.
Each ML550 voltage regulator output is connected to P72 to permit power plane current
measurements, which can in turn be used in power consumption calculations, recalling
that Power (P) = Voltage (V) x Current (I), and that in the case of the current sense resistor,
Current (I) = Sensed Voltage (V S )/0.010 Ω . The resulting power measurement equation is:
P = V x (V S /0.010) Watts
The ML550 +5V input is also connected through a current measurement resistor. The value
of the resistor (R201) is 5 m Ω . When measuring current using the +5V signals at P72,
V CC5_S+ and V CC5_S– , the power measurement equation is modified to:
P = V x (V S /0.005) Watts
Table 3-12 shows the power measurement header P72 connections of the voltage regulator
sense resistors. Refer to Figure 3-21, page 42 and Table 3-16, page 43 for complete P72
pinout details.
Table 3-12:
Power Measurement P72 Pinout
Power Plane
Regulator Nominal V OUT
P72 Pin Number
S+ S– MON
R SENSE
R (m Ω )
V CC5(1)
V CC3V3
V CC1V0
V CC2V5_VCCO
V CC2V5
V CC2V5_VAUX
J20
VR1
VR2
VR4
VR3
VR5
5.18V input
3.30V
1.00V
2.50V
2.50V
2.50V
25
17
1
9
13
5
26
18
2
10
14
6
24
19
3
11
15
7
R201
R387
R386
R385
R383
R384
5
10
10
10
10
10
Notes:
1. V CC5 power available on P72 pin 20.
2. P72 GND pins: 4, 8, 12, 16.
3. ML550 errata: Due to a layout component library error, the S+ and S– pin connections are reversed. To
obtain a positive DVM reading, apply the negative lead to the S+ pin, and the positive lead to the S–
pin.
4. P72 is a 2 x 13 pin header (male) with pins on 0.1-inch centers.
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
www.xilinx.com
33
相关PDF资料
PDF描述
HW-V5-ML555-G BOARD EVAL FOR VIRTEX-5 ML555
HW-V5-ML561-UNI-G EVALUATION PLATFORM VIRTEX-5
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相关代理商/技术参数
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