参数资料
型号: HW-V5-ML550-UNI-G
厂商: Xilinx Inc
文件页数: 43/88页
文件大小: 0K
描述: EVALUATION PLATFORM VIRTEX-5
产品变化通告: Adapter Replacement 23/May/2008
Development Systems Discontinuation 26/Apr/2011
标准包装: 1
系列: Virtex®-5 LXT
类型: FPGA
适用于相关产品: XC5VLX50T-FFG1136
所含物品: 开发平台,电源,回送板,小型闪存卡,软件和文档
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R
ML550 System Monitor and Power Monitor Support
Power Monitor Circuitry
The ML550 hosts a 2 x 13 0.1-inch male header connector which provides test points for the
ML550 power regulators as shown in Table 3-16 .
Table 3-16:
Power Monitor Connector P72 Pinout
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Signal Name
VCC1V0_VINT_S+
VCC1V0_VINT_S–
VCC1V0_VINT_MON
Dgnd
VCC2V5_VAUX_S+
VCC2V5_VAUX_S–
VCC2V5_VAUX_MON
Dgnd
VCC2V5_VCCO_S+
VCC2V5_VCCO_S–
VCC2V5_VCCO_MON
Dgnd
VCC2V5_S+
VCC2V5_S–
VCC2V5_MON
Dgnd
VCC3V3_SYS_S+
VCC3V3_SYS_S–
VCC3V3_SYS_MON
VCC5
NC
NC
NC
VCC5_MON
VCC5_S+
VCC5_S–
R KELVIN REF
R386
R386
R386
R384
R384
R384
R385
R385
R385
R383
R383
R383
R387
R387
R387
R201
R201
R201
Schematic
20, 23
20, 23
20, 23
20
20, 24
20, 24
20, 24
20
20, 22
20, 22
20, 22
20
20, 22
20, 22
20, 22
20
20, 24
20, 24
20, 24
19, 20
20
20
20
19,20
19,20
19,20
Notes
S– actual
S+ actual
S– actual
S+ actual
S– actual
S+ actual
S– actual
S+ actual
S– actual
S+ actual
S– actual
S+ actual
The regulator outputs are connected to a series Kelvin resistor, which is then connected to
the target power plane. ML550 voltage regulator topology is discussed in detail in sections
“Voltage Regulators (TI PTH05000),” page 29 and “Power Monitor Connector,” page 32 . A
summary of the regulator connections to P72 is given in Table 3-12, page 33 .
Note: As indicated in Note 3 beneath Table 3-12 , the S+ and S– pins of P72 are reversed.
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
43
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