参数资料
型号: IBM25PPC750-DB0M2500
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360
封装: 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件页数: 13/42页
文件大小: 496K
代理商: IBM25PPC750-DB0M2500
Page 20
v 3.2
Datasheet
7/15/99
PowerPC 750TM SCM RISC Microprocessor
Preliminary Copy
IEEE 1149.1 AC Timing Specications
Table 13provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 16, Figure 17,
Figure 18, and Figure 19. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
Figure 16 provides the JTAG clock input timing diagram.
Table 13. JTAG AC Timing Specications (Independent of SYSCLK)
See Table 2 for operating conditions, CL = 50pF
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
33.3
MHz
1
TCK cycle time
30
ns
2
TCK clock pulse width measured at 1.4V
15
ns
3
TCK rise and fall times
0
2
ns
4
Spec obsolete, intentionally omitted
5
TRST assert time
25
ns
1
6
Boundary-scan input data setup time
4
ns
2
7
Boundary-scan input data hold time
15
ns
2
8
TCK to output data valid
4
20
ns
3,5
9
TCK to output high impedance
3
19
ns
3,4
10
TMS, TDI data setup time
0
ns
11
TMS, TDI data hold time
12
ns
12
TCK to TDO data valid
2.5
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 16. JTAG Clock Input Timing Diagram
TCK
VM
1
2
3
VM
VM = Midpoint Voltage (1.4V)
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