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参数资料
| 型号： | IBM25PPC750-DB0M2500 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 27/42页 |
| 文件大小： | 496K |
| 代理商： | IBM25PPC750-DB0M2500 |
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7/15/99
v 3.2
Datasheet
Page 33
Preliminary Copy
PowerPC 750TM SCM RISC Microprocessor
Pull-up Resistor Requirements
The 750 requires high resistive (weak: 10K
) pull-up resistors on several control signals of the bus interface
to maintain the control signals in the negated state after they have been actively negated and released by the
750 or other bus masters. These signals are: TS, ABB, DBB, and ARTRY.
In addition, the 750 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7K
- 1K
) if it is used by the system. This signal is CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any mas-
ter and may float in the high-impedance state for relatively long periods of time. Since the 750 must continu-
ally monitor these signals for snooping, this float condition may cause excessive power draw by the input
receivers on the 750 or by other receivers in the system. It is recommended that these signals be pulled up
through weak (10K
) pull-up resistors or restored in some manner by the system, The snooped address and
transfer attribute inputs are: A[0-31], AP[0-3], TT[0-4], TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and do not require
pull-up resistors on the data bus. Other data bus receivers in the system, however, may require pull-ups, or
that those signals be otherwise driven by the system during inactive periods. The data bus signals are: DH[0-
31], DL[0-31], and DP[0-7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, than all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
No pull-up resistors are normally required for the L2 interface.
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相关代理商/技术参数 |
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|---|---|
| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FL-GR0124V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FL-GR0133T | 制造商:IBM 功能描述:IBMIBM25PPC750FL-GR0133T CSOI9SG LOGIC P |
| IBM25PPC750FL-GR0133V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FL-GR1024T | 制造商:IBM 功能描述: |
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