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参数资料
| 型号： | IBM25PPC750-DB0M2500 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 38/42页 |
| 文件大小： | 496K |
| 代理商： | IBM25PPC750-DB0M2500 |
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7/15/99
v 3.2
Datasheet
Page 5
Preliminary Copy
PowerPC 750TM SCM RISC Microprocessor
- 4 instruction BAT's and 4 data BATs.
- Virtual memory support for up to 4 exabytes (252) virtual memory.
- Real memory support for up to 4 gigabytes (232) of physical memory.
Level 2 (L2) cache interface
- Internal L2 cache controller and 4K-entry tags; external data SRAMs.
- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support.
- Copy-back or write-through data cache (on a page basis, or for all L2).
- 64-byte(256K/512K) and 128-byte (l-Mbyte) sectored line size.
- Supports ow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst
SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs
- Design supports Core-to-L2 frequency divisors of
÷1, ÷1.5, ÷2, ÷2.5, and ÷3.
However, this specification supports the L2 frequency range specified in Section, “L2 Clock AC Spec-
ifications” on page 15. For higher L2 frequencies not supported in this document, please contact your
IBM marketing representative.
Bus interface
- Compatible with 60x processor interface.
- 32-bit address bus.
- 64-bit data bus.
- Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x,7.5x, and 8x supported.
Integrated power management
- Low-power 2.7/3.3-volt design.
- Three static power saving modes: doze, nap, and sleep.
- Automatic dynamic power reduction when internal functional units are idle.
Integrated Thermal Management Assist Unit
- On-chip thermal sensor and control logic.
- Thermal Management Interrupt for software regulation of junction temperature.
Testability
- LSSD scan design.
- JTAG interface.
Reliability and serviceability; Parity checking on 60x and L2 cache buses
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相关代理商/技术参数 |
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| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
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