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参数资料
| 型号： | IBM25PPC750-DB0M2500 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 24/42页 |
| 文件大小： | 496K |
| 代理商： | IBM25PPC750-DB0M2500 |
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Page 30
v 3.2
Datasheet
7/15/99
PowerPC 750TM SCM RISC Microprocessor
Preliminary Copy
Table 16 provides sample core-to-L2 frequencies.
PLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the 750 to provide power to the clock generation
phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the
power supplied to the AVDD input signal should be filtered using a circuit similar to the one shown in
Figure 22. The circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much
noise as possible. An identical but separate circuit should be placed as close as possible to the L2AVDD pin.
Table 16. Sample Core-to-L2 Frequencies1
Core Frequency
(MHz)
÷1
÷1.5
÷2
÷2.5
÷3
200
—
133.3
100
80
—
225
—
112.5
90
—
233
—
116.5
93.2
—
250
—
125
100
83.3
266
—
133
106.4
88.6
275
—
110
91.7
300
—
120
100
Note:
1. Although the 750 is designed for L2 bus ratios of 1:1, 1.5:1, 2:1, 2.5:1, and 3:1, this specication supports the L2 fre-
quency range specied in Section, “L2 Clock AC Specications” on page 15. For higher L2 frequencies not supported in
this document, please contact your IBM marketing representative.
Figure 22. PLL Power Supply Filter Circuit
VDD
AVDD (or L2AVDD)
10 Ohm
10 mF
0.1 mF
GND
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