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参数资料
| 型号： | ICS5342 |
| 元件分类： | 显示控制器 |
| 英文描述： | PALETTE-DAC DSPL CTLR, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 9/36页 |
| 文件大小： | 1017K |
| 代理商： | ICS5342 |
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ICS5342
GENDAC
17
Frequency Generators
The ICS5342 clock synthesizer can be reprogrammed through
the microprocessor interface for any set of frequencies. This
is done by writing appropriate values to the PLL Parameter
Register Bank (See following table: “PLL Parameter Regis-
ters”).
PLL Address Registers
The address of the parameter register is written to the PLL ad-
dress registers before accessing the parameter register. This
register is accessed by register select pins RS2-RS0 = 100 or
111.
PLL Parameters Registers
There are sixteen registers in the PLL parameter register (ta-
ble 5). Registers 00 to 07 are for the CLK0 selectable frequen-
cy list, Register 0A and 0B for CLK1 programmable
frequency and register 0E is the PLL control register.
PLL Control Register
Bits in this register determine internal or external CLK0 se-
lect.
Bit 7,6, 3 Reserved, set to ‘0’ for future compatibility.
Bit 5
Enable Internal Clock Select (INCS) for CLK0.
When this bit is set to 1, the CLK0 output fre-
quency is selected by bits 2-0 in this register.
External pins CS0-CS2 are ignored.
Bit 4
Clk1 Select when this bit is set to 0, fA is
selected. When it is set to 1, fB is selected. The
default is 0 for fA selected at power up.
Bit 2 - 0
Internal Clock Select for CLK0 (INCS). These
three bits select the CLK0 output frequency if bit
5 of this register is on. They are interpreted as an
octal number, n, that selects fn. Default selects f0.
PLL Data Registers
The CLK0 and CLK1 output frequency is determined by the
parameter values in this register. These are two-byte registers;
the first byte is the M-byte and the second the N-byte.
M-Byte PLL Parameter Input
The M-byte has a 7-bit value (1-127) which is the feedback
divider of the PLL.
N-Byte PLL Parameter Input
The N-byte contains two parameter values. N1 sets a 5-bit val-
ue (1-31) for the input pre scalar and N2 is a 2-bit code for se-
lecting 1, 2, 4, or 8 post divide clock output.
PLL Address Register
76543210
PLL Register Adr.
76543210
PLL Parameter Registers
Index
R/W
Register
00
R/W
CLK0 f0 PLL Parameters
(2 bytes)
01
R/W
CLK0 f1 PLL Parameters
(2 bytes)
02
R/W
CLK0 f2 PLL Parameters
(2 bytes)
03
R/W
CLK0 f3 PLL Parameters
(2 bytes)
04
R/W
CLK0 f4 PLL Parameters
(2 bytes)
05
R/W
CLK0 f5 PLL Parameters
(2 bytes)
06
R/W
CLK0 f6 PLL Parameters
(2 bytes)
07
R/W
CLK0 f7 PLL Parameters
(2 bytes)
08
R/-
(Reserved) = 0
(2 bytes
09
R/W
CLK1 fA PLL
(2 bytes)
0A
R/W
CLK1 fB PLL
(2 bytes)
0B
R/W
(Reserved) = 0
(2 bytes
0C
R/-
(Reserved) = 0
(2 bytes)
0D
R/-
(Reserved) = 0
(2 bytes)
0E
R/W
PLL Control Register
(1-byte)
0F
R/-
(Reserved) = 0
(2 bytes)
PLL Control Register
76543210
(RV)=
0
(RV)=
0
ENBL
INCS
CLK1
SEL
(RV)=
0
Internal Select
XXX
M-Byte
7
6543210
Reserved
= 0
M-Divider Value
XXXXXXX
N-Byte PLL Parameter Input
7
6543210
Reserved
= 0
N2 - Code
N1-Divider Value
XXXXXXX
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS5342-1 | 制造商:ICS 制造商全称:ICS 功能描述:Analog IC |
| ICS5342-2 | 制造商:ICS 制造商全称:ICS 功能描述:Analog IC |
| ICS5342-3 | 制造商:ICS 制造商全称:ICS 功能描述:Analog IC |
| ICS5342ADD | 制造商:ICS 制造商全称:ICS 功能描述:Addendum to ICS5342 Data Sheet |
| ICS5342V | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Peripheral IC |
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