参数资料
型号: IDT70T3339S200BCG
厂商: IDT, Integrated Device Technology Inc
文件页数: 5/27页
文件大小: 0K
描述: IC SRAM 9MBIT 200MHZ 256BGA
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 9M(512K x 18)
速度: 200MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70T3339S200BCG
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Pin Names
Industrial and Commercial Temperature Ranges
Left Port
CE 0L , CE 1L
R/ W L
OE L
Right Port
CE 0R , CE 1R
R/ W R
OE R
Names
Chip Enables (Input) (6)
Read/Write Enable (Input)
Output Enable (Input)
A 0R - A 18R
A 0L - A 18L
(5)
(5)
Address (Input)
I/O 0L - I/O 17L
CLK L
PL/ FT L
ADS L
CNTEN L
REPEAT L
UB L
LB L
V DDQL
OPT L
ZZ L
I/O 0R - I/O 17R
CLK R
PL/ FT R
ADS R
CNTEN R
REPEAT R
UB R
LB R
V DDQR
OPT R
ZZ R
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat (3)
Upper Byte Enable (I/O 9 - I/O 17 ) (6)
Lower Byte Enable (I/O 0 - I/O 8 ) (6)
Power (I/O Bus) (3.3V or 2.5V) (1) (Input)
Option for selecting V DDQX (1,2) (Input)
Sleep Mode pin (4) (Input)
V DD
V SS
TDI
TDI
TCK
TMS
TRST
Power (2.5V) (1) (Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
NOTES:
1. V DD , OPT X , and V DDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT X selects the operating voltage levels for the I/Os and controls on that port.
If OPT X is set to V DD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V DDQX must be supplied at 3.3V. If OPT X is set to V SS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V DDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
INT L
COL L
INT R
COL R
Interrupt Flag (Output)
Collision Alert (Output)
5652 tbl 01
3. When REPEAT X is asserted, the counter will reset to the last valid address loaded
via ADS X .
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/ FT x and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Address A 18x is a NC for the IDT70T3319. Also, Addresses A 18x and A 17x are
NC's for the IDT70T3399.
6. Chip Enables and Byte Enables are double buffered when PL/ FT = V IH , i.e., the
signals take two cycles to deselect.
5
6.42
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