参数资料
型号: IDT70T3509MS133BP
厂商: IDT, Integrated Device Technology Inc
文件页数: 16/23页
文件大小: 0K
描述: IC SRAM 36MBIT 133MHZ 256BGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 36M(1M x 36)
速度: 133MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 256-BGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70T3509MS133BP
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs) (1)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
A 0 - A 18
An
t SA
A 19 (7)
INTERNAL (3)
ADDRESS
An (5)
An + 1
An + 2
An + 3
An + 4
t SAD t HAD
ADS
t SCN t HCN
CNTEN
t SD t HD
(5)
DATA IN
Dn
Dn + 1
Dn + 1
Dn + 2
Dn + 3
Dn + 4
(7)
WRITE
EXTERNAL
ADDRESS
WRITE WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5682 drw 17a
Timing Waveform of Counter Repeat (2,6)
t CYC2
CLK
t SA t HA
A 0 - A 18
An
t SA
A 19 (7)
INTERNAL (3)
ADDRESS
An
An+1
An+2
An+2
An
An+1
An+2
An+2
t SAD t HAD
ADS
t SW t HW
R/ W
t SCN t HCN
CNTEN
REPEAT
(4)
t SRPT t HRPT
t SD t HD
,
DATA IN
D 0
D 1
D 2
D 3
t CD1
DATA OUT
An
An+1
An+2
An+2
(7)
WRITE TO ADVANCE
ADS COUNTER
ADDRESS WRITE TO
An An+1
NOTES:
1. CE 0 , BE n , and R/ W = V IL ; CE 1 and REPEAT = V IH .
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
An+1
,
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
5682 drw 18a
2. CE 0 , BE n = V IL ; CE 1 = V IH .
3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH .
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II. A 19 must be in the appropriate state when using the REPEAT
function to guarantee the correct address location is loaded.
5. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
7. Address A 19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000 H through 7FFFF H the
value of a A 19 is 0, while for physical addresses 80000 H through FFFFF H the value of A 19 is 1. The user needs to keep track of the device counter and make
sure that A 19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation. As shown this
transition reflects An = 7FFFF H or FFFFF H .
16
6.42
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