参数资料
型号: IDT70T3509MS133BP
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/23页
文件大小: 0K
描述: IC SRAM 36MBIT 133MHZ 256BGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 36M(1M x 36)
速度: 133MHz
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 256-BGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70T3509MS133BP
IDT70T3509M
High-Speed 2.5V
Pin Names
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Left Port
CE 0L , CE 1L
R/ W L
OE L
A 0L - A 19L
I/O 0L - I/O 35L
CLK L
PL/ FT L
ADS L
CNTEN L
REPEAT L
BE 0L - BE 3L
V DDQL
OPT L
ZZ L
Right Port
CE 0R , CE 1R
R/ W R
OE R
A 0R - A 19R
I/O 0R - I/O 35R
CLK R
PL/ FT R
ADS R
CNTEN R
REPEAT R
BE 0R - BE 3R
V DDQR
OPT R
ZZ R
Names
Chip Enables (Input) (5)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat (3) (Input)
Byte Enables (9-bit bytes) (Input) (5)
Power (I/O Bus) (3.3V or 2.5V) (1) (Input)
Option for selecting V DDQX (1,2) (Input)
Sleep Mode pin (4) (Input)
V DD
V SS
TDI
TDO
TCK
TMS
Power (2.5V) (1) (Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
NOTES:
1. V DD , OPT X , and V DDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT X selects the operating voltage levels for the I/Os and controls on that port.
If OPT X is set to V DD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V DDQX must be supplied at 3.3V. If OPT X is set to V SS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V DDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
INT L
TRST
INT R
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
3. When REPEAT X is asserted, the counter will reset to the last valid address loaded
via ADS X .
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
5682 tbl 01
asserted. All static inputs, i.e., PL/ FT x and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundary scan not be operated during sleep mode.
5. Chip Enables and Byte Enables are double buffered when PL/ FT = V IH , i.e., the
signals take two cycles to deselect.
6.42
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