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参数资料
| 型号： | IDT70T653MS15BC8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/24页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18MBIT 15NS 256BGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 18M（512K x 36） |
| 速度： | 15ns |
| 接口： | 并联 |
| 电源电压： | 2.4 V ~ 2.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-CABGA（17x17） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70T653MS15BC8 |
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
RapidWrite Mode Write Cycle
Unlike other vendors' Asynchronous Random Access Memories,
the IDT70T653M is capable of performing multiple back-to-back write
operations without having to pulse the R/ W , CE , or BE n signals high
during address transitions. This RapidWrite Mode functionality allows the
system designer to achieve optimum back-to-back write cycle performance
without the difficult task of generating narrow reset pulses every cycle,
simplifying system design and reducing time to market.
During this new RapidWrite Mode, the end of the write cycle is now
defined by the ending address transition, instead of the R/ W or CE or BE n
transition to the inactive state. R/ W , CE , and BE n can be held active
throughout the address transition between write cycles. Care must be
Industrial and Commercial Temperature Ranges
taken to still meet the Write Cycle time (t WC ), the time in which the Address
inputs must be stable. Input data setup and hold times (t DW and t DH ) will
now be referenced to the ending address transition. In this RapidWrite
Mode the I/O will remain in the Input mode for the duration of the operations
due to R/ W being held low. All standard Write Cycle specifications must
be adhered to. However, t AS and t WR are only applicable when switching
between read and write operations. Also, there are two additional
conditions on the Address Inputs that must also be met to ensure correct
address controlled writes. These specifications, the Allowable Address
Skew (t AAS ) and the Address Rise/Fall time (t ARF ), must be met to use the
RapidWrite Mode. If these conditions are not met there is the potential for
inadvertent write operations at random intermediate locations as the
device transitions between the desired write addresses.
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle (1,3)
t WC
CE or SEM
t EW
ADDRESS
(6)
t WC
(2)
(4)
t WC
BE n
t WR
R/ W
t WP
(5)
t WZ
(5)
t OW
DATA OUT
t DW
t DH
t DW
t DH
t DW
t DH
DATA IN
5679 drw 08
NOTES:
1. OE = V IL for this timing waveform as shown. OE may equal V IH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (t EW or t WP ) of a CE = V IL, BE n = V IL , and a R/ W = V IL for memory array writing cycle. The last transition LOW of CE , BE n, and
R/ W initiates the write sequence. The first transition HIGH of CE , BE n, and R/ W terminates the write sequence.
3. If the CE or SEM = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . t EW must be met for either condition. CE = V IL when CE 0 = V IL
and CE 1 = V IH . CE = V IH when CE 0 = V IH and/or CE 1 = V IL .
12
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