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| 型号： | IDT82V2042EPFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 32/83页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 2CH SHORT 80TQFP |
| 标准包装： | 45 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 82V2042EPFG |
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IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
38
December 12, 2005
3.11 MCLK AND TCLK
3.11.1 MASTER CLOCK (MCLK)
MCLK is an independent, free-running reference clock. MCLK is 1.544
MHzforT1/J1applicationsand2.048MHzinE1mode.Thisreferenceclock
is used to generate several internal reference signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during Transmit All Ones (TAOS), all zeros, PRBS/
QRSS and Inband Loopback code if it is selected as the reference
clock. For ATAO and AIS, MCLK is always used as the reference
clock.
Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS/QRSS in hardware control mode.
Figure-19 shows the chip operation status in different conditions of
MCLK and TCLKn. The missing of MCLK will set all the TTIPn/TRINGn to
high impedance state.
3.11.2 TRANSMIT CLOCK (TCLK)
TCLKn is used to sample the transmit data on TDn/TDPn, TDNn. The
active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 04H...).
During Transmit All Ones, PRBS/QRSS patterns or Inband Loopback
Code, either TCLKn or MCLK can be used as the reference clock. This is
selected by the PATT_CLK bit (MAINT0, 0CH...).
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0CH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0CH) is set to ‘1’.
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 16H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
isnotusingMCLK totransmitinternal patterns (TAOS,AllZeros,PRBSand
in-band loopback code). When TCLK is detected again, TCLK_LOS bit
(STAT0, 16H...) will be cleared. The reference frequency to detect a TCLK
loss is derived from MCLK.
Figure-19 TCLK Operation Flowchart
both the transmitters high
impedance
yes
MCLK=H/L?
normal operation
Clocked
TCLKn status?
L/H
clocked
generate transmit clock loss
interrupt if not masked in
software control mode;
transmitter n high impedance
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| IDT82V2042EPFG8 | 功能描述:IC LIU T1/J1/E1 2CH SHORT 80TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2044 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2044BB | 功能描述:IC LIU T1/E1 QUAD SHORT 160-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2044BBG | 功能描述:IC LIU T1/E1 QUAD SHORT 160-BGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2044DA | 功能描述:IC LIU T1/E1 QUAD SHORT 144-TQFP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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