参数资料
型号: IDT82V2042EPFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 8/83页
文件大小: 0K
描述: IC LIU T1/J1/E1 2CH SHORT 80TQFP
标准包装: 45
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-TQFP(14x14)
包装: 托盘
其它名称: 82V2042EPFG
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION
16
December 12, 2005
JA1
I
16
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only used
in hardware control mode)
00 = JA is disabled
01= JA in receiver, broad bandwidth, FIFO=64 bits
10 = JA in receiver, narrow bandwidth, FIFO=128 bits
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
In software control mode, this pin should be connected to ground.
JA0
I
17
See above.
MONT2
I
18
MONT2: Receive Monitor gain select for channel 2
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
MONT1
I
19
MONT1: Receive Monitor gain select for channel 1
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
RST
I21
RST: Hardware Reset
The chip is forced to reset state if a low signal is input on this pin for more than 100ns. MCLK must be active during reset.
THZ
I
20
THZ: Transmitter Driver High Impedance Enable
This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while a high
level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not affected by
this signal.
JTAG Signals
TRST
I
Pullup
1
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure determin-
istic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
If JTAG is not used, this pin must be connected to ground.
TMS
I
Pullup
2
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal pull-
up resistor.
If JTAG is not used, this pin may be left unconnected.
TCK
I
3
TCK: JTAG Test Clock
This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while the
data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-state devices
contained in the test logic will retain their state indefinitely.
If JTAG is not used, this pin may be left unconnected.
TDO
O
4
TDO: JTAG Test Data Output
This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test logic.
The data on TDO is clocked out of the device on the falling edge of TCK.
If JTAG is not used, this pin should be left unconnected.
TDI
I
Pullup
5
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pull-up resistor. The data on TDI is
clocked into the device on the rising edge of TCK.
If JTAG is not used, this pin may be left unconnected.
Power Supplies and Grounds
VDDIO
-
7,40
3.3 V I/O power supply
GNDIO
-
8,39
I/O ground
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
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IDT82V2044BBG 功能描述:IC LIU T1/E1 QUAD SHORT 160-BGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器,接收器,收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP(0.173",4.40mm 宽) 供应商设备封装:16-TSSOP 包装:带卷 (TR)
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