- 您现在的位置：买卖IC网 > PDF目录377488 > IDT82V3288 (Integrated Device Technology, Inc.) WAN PLL PDF资料下载
参数资料
| 型号： | IDT82V3288 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | WAN PLL |
| 中文描述： | 广域网锁相环 |
| 文件页数： | 22/170页 |
| 文件大小： | 1053K |
| 代理商： | IDT82V3288 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页
IDT82V3288
WAN PLL
Functional Description
22
June 22, 2006
3.4
INPUT CLOCK PRE-DIVIDER
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz.
For IN1 and IN2, the DPLL required frequency is fixed to 8 kHz (i.e.,
the corresponding IN_FREQ[3:0] bits are ‘0000’). The 8 kHz clock is
extracted from the composite clock and the Pre-Divider is bypassed
automatically.
For IN3 ~ IN14, the DPLL required frequency is set by the corre-
sponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
Each Pre-Divider consists of a HF (High Frequency) Divider (only
available for IN5 and IN6), a DivN Divider and a Lock 8k Divider, as
shown in
Figure 3
.
The HF Divider, which is only available for IN5 and IN6, should be
used when the input clock is higher than (
>
) 155.52 MHz. The input
clock can be divided by 4, 5 or can bypass the HF Divider, as deter-
mined by the IN5_DIV[1:0]/IN6_DIV[1:0] bits correspondingly.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used for INn (3
≤
n
≤
14), the division factor
setting should observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
The DivN Divider can only divide the input clock whose frequency is
lower than (
<
) 155.52 MHz.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the IN3 ~ IN14 pins and the DPLL required
clock. Here is an example:
The input clock on the IN6 pin is 622.08 MHz; the DPLL required
clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of register IN6
to ‘0010’. Do the following step by step to divide the input clock:
1. Use the HF Divider to divide the clock down to 155.52 MHz:
622.08 ÷ 155.52 = 4, so set the IN6_DIV[1:0] bits to ‘01’;
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN6_CNFG to ‘1’ and the
LOCK_8K bit in Register IN6_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Figure 3. Pre-Divider for An Input Clock
Input Clock INn
(14>n>3)
DivN Divider
Lock 8k Divider
HF Divider
(for IN5 & IN6 only)
Pre-Divider
IN5_DIV[1:0] bits / IN6_DIV[1:0] bits
DIRECT_DIV bit
LOCK_8K bit
DPLL required clock
相关PDF资料 |
PDF描述 |
|---|---|
| IDT82V3288BC | WAN PLL |
| IDT82V3288BCG | WAN PLL |
| IDT85304-01 | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| IDT85304 | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| IDT88P8344 | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3288BC | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3288BCG | 功能描述:IC PLL WAN 3E STRATUM 2 208CABGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3352 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
| IDT82V3355 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
| IDT82V3355DKG | 功能描述:IC PLL WAN SYNC ETH 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
发布紧急采购，3分钟左右您将得到回复。