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参数资料
型号： IMSH2GU13A1F1C-08D
厂商： QIMONDA AG
元件分类： DRAM
英文描述： 256M X 64 DDR DRAM MODULE, DMA240
封装： GREEN, UDIMM-240
文件页数： 10/49页
文件大小： 986K
代理商： IMSH2GU13A1F1C-08D
IMSH[1G/2G][U/E]x3A1F1C(T)
DDR3 Unbuffered DIMM
Advance Internet Data Sheet
Rev. 0.63, 2008-08
18
03052008-R2G5-2FN2
TABLE 14
DDR3-1333 Speed Bins and Operating Conditions
Speed Bin
DDR3-1333G
DDR3-1333H
Unit
Note
CL-nRCD-nRP
8-8-8
9-9-9
QAG Partnumber Extension
-13G
-13H
Parameter
Symbol
Min.
Max.
Min.
Max.
Internal read command to first data
t
AA
12.0
20.0
13.5
20.0
ns
1)
1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.
ACT to internal read or write delay time
t
RCD
12.0
—
13.5
—
ns
1)
PRE command period
t
RP
12.0
—
13.5
—
ns
1)
ACT to ACT or REF command period
t
RC
48.0
—
49.5
—
ns
1)
Supported CL Settings
Sup_CL
5, 6, 7, 8, 9, 10
6, 8, 9, 10
n
CK
1)
Supported CWL Settings
Sup_CWL
5, 6, 7
n
CK
1)
Average Clock Period with CL = 5; CWL = 5
t
CK.AVG.CL05.CWL05
2.5
3.3
RESERVED
ns
1)2)
2) Max. limits are exclusive. E.g. if
t
CK.AVG.MAX value is 2.5 ns, tCK.AVG needs to be < 2.5 ns.
Average Clock Period with CL = 5; CWL = 6
t
CK.AVG.CL05.CWL06
RESERVED
ns
1)2)
Average Clock Period with CL = 5; CWL = 7
t
CK.AVG.CL05.CWL07
RESERVED
ns
1)2)
Average Clock Period with CL = 6; CWL = 5
t
CK.AVG.CL06.CWL05
2.5
3.3
2.5
3.3
ns
1)2)
Average Clock Period with CL = 6; CWL = 6
t
CK.AVG.CL06.CWL06
RESERVED
ns
1)2)
Average Clock Period with CL = 6; CWL = 7
t
CK.AVG.CL06.CWL07
RESERVED
ns
1)2)
Average Clock Period with CL = 7; CWL = 5
t
CK.AVG.CL07.CWL05
RESERVED
ns
1)2)
Average Clock Period with CL = 7; CWL = 6
t
CK.AVG.CL07.CWL06
1.875
2.5
RESERVED
ns
1)2)
Average Clock Period with CL = 7; CWL = 7
t
CK.AVG.CL07.CWL07
RESERVED
ns
1)2)
Average Clock Period with CL = 8; CWL = 5
t
CK.AVG.CL08.CWL05
RESERVED
ns
1)2)
Average Clock Period with CL = 8; CWL = 6
t
CK.AVG.CL08.CWL06
1.875
2.5
1.875
2.5
ns
1)2)
Average Clock Period with CL = 8; CWL = 7
t
CK.AVG.CL08.CWL07
1.5
1.875
RESERVED
ns
1)2)
Average Clock Period with CL = 9; CWL = 5
t
CK.AVG.CL09.CWL05
RESERVED
ns
1)2)
Average Clock Period with CL = 9; CWL = 6
t
CK.AVG.CL09.CWL06
RESERVED
ns
1)2)
Average Clock Period with CL = 9; CWL = 7
t
CK.AVG.CL09.CWL07
1.5
1.875
1.5
1.875
ns
1)2)
Average Clock Period with CL = 10; CWL = 5
t
CK.AVG.CL10.CWL05
RESERVED
ns
1)2)
Average Clock Period with CL = 10; CWL = 6
t
CK.AVG.CL10.CWL06
RESERVED
ns
1)2)
Average Clock Period with CL = 10; CWL = 7
t
CK.AVG.CL10.CWL07
1.5
1.875
1.5
1.875
ns
1)2)
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