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参数资料
| 型号： | IMSH2GU13A1F1C-08D |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 256M X 64 DDR DRAM MODULE, DMA240 |
| 封装： | GREEN, UDIMM-240 |
| 文件页数： | 13/49页 |
| 文件大小： | 986K |
| 代理商： | IMSH2GU13A1F1C-08D |
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IMSH[1G/2G][U/E]x3A1F1C(T)
DDR3 Unbuffered DIMM
Advance Internet Data Sheet
Rev. 0.63, 2008-08
20
03052008-R2G5-2FN2
Average Clock Period
with CL = 8; CWL = 6
t
CK.AVG.CL08.CWL06
1.875
2.5
1.875
2.5
1.875
2.5
1.875
2.5
ns
Average Clock Period
with CL = 8; CWL = 7
t
CK.AVG.CL08.CWL07
1.5
1.875
1.5
1.875
RESERVED
ns
Average Clock Period
with CL = 8; CWL = 8
t
CK.AVG.CL08.CWL08
1.25
1.5
RESERVED
ns
Average Clock Period
with CL = 9; CWL = 5
t
CK.AVG.CL09.CWL05
RESERVED
ns
Average Clock Period
with CL = 9; CWL = 6
t
CK.AVG.CL09.CWL06
RESERVED
ns
Average Clock Period
with CL = 9; CWL = 7
t
CK.AVG.CL09.CWL07
1.5
1.875
1.5
1.875
1.5
1.875
RESERVED
ns
Average Clock Period
with CL = 9; CWL = 8
t
CK.AVG.CL09.CWL08
1.25
1.5
1.25
1.5
RESERVED
ns
Average Clock Period
with CL = 10; CWL = 5
t
CK.AVG.CL10.CWL05
RESERVED
ns
Average Clock Period
with CL = 10; CWL = 6
t
CK.AVG.CL10.CWL06
RESERVED
ns
Average Clock Period
with CL = 10; CWL = 7
t
CK.AVG.CL10.CWL07
1.5
1.875
1.5
1.875
1.5
1.875
1.5
1.875
ns
Average Clock Period
with CL = 10; CWL = 8
t
CK.AVG.CL10.CWL08
1.25
1.5
1.25
1.5
1.25
1.5
RESERVED
ns
Average Clock Period
with CL = 11; CWL = 5
t
CK.AVG.CL11.CWL05
RESERVED
ns
Average Clock Period
with CL = 11; CWL = 6
t
CK.AVG.CL11.CWL06
RESERVED
ns
Average Clock Period
with CL = 11; CWL = 7
t
CK.AVG.CL11.CWL07
RESERVED
ns
Average Clock Period
with CL = 11; CWL = 8
t
CK.AVG.CL11.CWL08
1.25
1.5
1.25
1.5
1.25
1.5
1.25
1.5
ns
1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.
2) Max. limits are exclusive. E.g. if
t
CK.AVG.MAX value is 2.5 ns, tCK.AVG needs to be < 2.5 ns.
Speed Bin
DDR3-1600G
DDR3-1600H
DDR3-1600J
DDR3-1600K
Unit
Note
CL-nRCD-nRP
8-8-8
9-9-9
10-10-10
11-11-11
QAG Partnumber Extension
-16G
-16H
-16J
-16K
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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