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| 型号： | IMSH2GU13A1F1C-08D |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 256M X 64 DDR DRAM MODULE, DMA240 |
| 封装： | GREEN, UDIMM-240 |
| 文件页数： | 8/49页 |
| 文件大小： | 986K |
| 代理商： | IMSH2GU13A1F1C-08D |
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IMSH[1G/2G][U/E]x3A1F1C(T)
DDR3 Unbuffered DIMM
Advance Internet Data Sheet
Rev. 0.63, 2008-08
16
03052008-R2G5-2FN2
4
Speed Bins and Timing Parameters
AC timings are provided with CK/CK and DQS/DQS
differential slew rate of 2.0 V/ns. Timings are further provided
for calibrated OCD drive strength. The CK/CK input reference
level (for timing referenced to CK / CK) is the point at which
CK and CK cross.The DQS/DQS reference level (for timing
referenced to DQS/DQS) is the point at which DQS and DQS
cross.Inputs are not recognized as valid until
V
REF stabilizes.
During the period before
V
REF.CA and VREFDQ stabilizes, CKE
= 0.2 x
V
DDQ is recognized as low. The output timing reference
voltage level is
V
TT.For details of all relevant AC timing
parameters see the QIMONDA DDR3 component datasheet.
4.1
Speed Bins
The following tables show DDR3 speed bins and relevant
timing parameters. Other timing parameters are provided in
the following chapter.
The absolute specification for all speed bins is
T
OPER and
V
DD = VDDQ = 1.5 V +/-0.075 V. In addition the following
general notes apply.
General Notes for Speed Bins:
The CL setting and CWL setting result in
t
CK.AVG.MIN and
t
CK.AVG.MAX requirements. When making a selection of
t
CK.AVG, both need to be fulfiled: Requirements from CL
setting as well as requirements from CWL setting
t
CK.AVG.MIN limits: Since CAS Latency is not purely analog -
data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be provided. An
application should use the next smaller standard
t
CK.AVG
value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL
[nCK] =
t
AA [ns] / tCK.AVG [ns], rounding up to the next
‘Supported CL’
t
CK.AVG.MAX limits: Calculate tCK.AVG = tAA.MAX /
CLSELECTED and round the resulting
t
CK.AVG down to the
next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns
or 1.25 ns). This result is
t
CK.AVG.MAX corresponding to
CLSELECTED
‘Reserved’ settings are not allowed. User must program a
different value
Any DDR3-1066 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization
Any DDR3-1333 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization
Any DDR3-1600 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization
TABLE 12
DDR3-800 Speed Bins and Operating Conditions
Speed Bin
DDR3-800D
DDR3-800E
Unit
Note
CL-
n
RCD-nRP
5-5-5
6-6-6
QAG Partnumber Extension
-08D
-08E
Parameter
Symbol
Min.
Max.
Min.
Max.
Internal read command to first data
t
AA
12.5
20.0
15.0
20.0
ns
1)
ACT to internal read or write delay time
t
RCD
12.5
—
15.0
—
ns
PRE command period
t
RP
12.5
—
15.0
—
ns
ACT to ACT or REF command period
t
RC
50.0
—
52.5
—
ns
Supported CL Settings
Sup_CL
5, 6
6
n
CK
Supported CWL Settings
Sup_CWL
5
n
CK
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