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参数资料
| 型号： | IMSH2GU13A1F1C-08D |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 256M X 64 DDR DRAM MODULE, DMA240 |
| 封装： | GREEN, UDIMM-240 |
| 文件页数： | 23/49页 |
| 文件大小： | 986K |
| 代理商： | IMSH2GU13A1F1C-08D |
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IMSH[1G/2G][U/E]x3A1F1C(T)
DDR3 Unbuffered DIMM
Advance Internet Data Sheet
Rev. 0.63, 2008-08
3
03052008-R2G5-2FN2
1Overview
This chapter gives an overview of the 240–pin Unbuffered DDR3 Dual-In-Line memory modules product family and describes
its main characteristics.
1.1
Features
240-pin 8-Byte DDR3 SDRAM unbuffered dual-in-line
memory modules.
Module organization: 128M
× 64, 256M × 64, 128M × 72,
256M
× 72
Chip organization: 128M
× 8
PC3-12800, PC3-10600, PC3-8500 and PC3-6400
module speed grades.
2GB, 1GB, 512MB modules built with 1Gb DDR3 SDRAMs
in packages PG-TFBGA-78.
DDR3 SDRAMs with a single 1.5 V (
± 0.075 V) power
supply.
Asynchronous Reset.
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
Refresh. Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
Serial Presence Detect with EEPROM.
Thermal sensor functionality supported.
UDIMM dimensions: 133.35 mm x 30 mm.
Based on standard reference raw cards: 'A', 'B', 'D', and 'E'.
RoHS compliant products
1).
TABLE 1
Performance Table for DDR3–1600 and DDR3–1333
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products .
QAG Speed Code
–16J
–13G
–13H
Unit
Note
1)
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting. For details, refer to Chapter 4.1 Speed Bins.
Module Speed Bin
PC3
–12800J
–10600G
–10600H
Device Speed Bin
DDR3
–1600J
–1333G
–1333H
CL-
n
RCD-nRP
10-10-10
8-8-8
9-9-9
CL and CWL settings for maximum clock
frequency
CL = 10
CWL = 8
CL = 8
CWL = 7
CL = 9
CWL = 7
MHz
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
800
1600
667
1333
667
1333
MHz
Mb/s
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
667
1333
533
1066
533
1066
MHz
Mb/s
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