参数资料
| 型号： | IP-NCO |
| 厂商： | Altera |
| 文件页数： | 38/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 初始许可证 |
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4–6
Chapter 4: Functional Description
Functional Description
In an NCO, the CORDIC algorithm computes the sine and cosine of an input phase
value by iteratively shifting the phase angle to approximate the cartesian coordinate
values for the input angle. At the end of the CORDIC iteration, the x and y coordinates
for a given angle represent the cosine and sine of that angle, respectively ( Figure 4–3 ).
Figure 4–3. CORDIC Rotation for Sine & Cosine Calculation
y
d?
dy
sin ?
?
cos ?
x
dx
With the NCO MegaCore function, you can select parallel (unrolled) or serial
(iterative) CORDIC architectures:
■
■
You an use the parallel CORDIC architecture to create a very high-performance,
high-precision oscillator—implemented entirely in logic elements—with a
throughput of one output sample per clock cycle. With this architecture, there is a
new output value every clock cycle.
The serial CORDIC architecture uses fewer resources than the parallel CORDIC
architecture. However, its throughput is reduced by a factor equal to the
magnitude precision. For example, if you select a magnitude precision of N bits in
the NCO MegaCore function, the output sample rate and the Nyquist frequency is
reduced by a factor of N . This architecture is implemented entirely in logic
elements and is useful if your design requires low frequency, high precision
waveforms. With this architecture, the adder stages are stored internally and a
new output value is produced every N clock cycles.
For more information about the parallel and serial CORDIC architectures, refer to
“Implementation Tab - CORDIC Algorithm” on page 3–5 .
Multiplier-Based Architecture
The multiplier-based architecture uses multipliers to reduce memory usage. You can
choose to implement the multipliers in either:
NCO MegaCore Function
User Guide
■
■
Logic elements (Cyclone series of devices) or combinational ALUTs (Stratix series
of devices).
Dedicated multiplier circuitry (for example, dedicated DSP blocks) in device
families that support this feature (Stratix V, Stratix IV, Stratix III, Stratix II, Stratix
GX, Stratix, or Arria GX devices).
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
| IP-RIOPHY | IP RAPID I/O |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-NIOS | 功能描述:开发软件 Nios II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPO-002-VSF-LF | 制造商:PROXISTOR AB ELECTRONIC 功能描述:PROXIMITY SWITCH, PNP; Sensor Input:Inductive; Sensing Range Max:2mm; Supply Voltage DC Min:10V; Supply Voltage DC Max:30V; SVHC:No SVHC (19-Dec-2012); External Depth:10.5mm; External Length / Height:16.5mm; External Width:30mm; |
| IPOD TOUCH4-C-B | 制造商:Distributed By MCM 功能描述:Apple® iPod Black Touch 4th Gen Digitizer + Glass 制造商:Distributed By MCM 功能描述:APPLE IPOD TOUCH DIGITIZER BLACK |
| IPOD TOUCH4-C-W | 制造商:Distributed By MCM 功能描述:APPLE IPOD TOUCH DIGITIZER WHITE 制造商:Distributed By MCM 功能描述:Apple® iPod White Touch 4th Gen Digitizer + Glass |
| IPP015N04N G | 功能描述:MOSFET OptiMOS 3 PWR TRANST 40V 120A RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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