参数资料
| 型号： | IP-NCO |
| 厂商： | Altera |
| 文件页数： | 48/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 初始许可证 |
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A–2
Appendix A: Example Multichannel Design
Multichannel Design
1. Browse to the appropriate example design directory. There is a choice between
VHDL and Verilog HDL files.
2. Create a new Quartus II project in the example design directory.
3. Add the Verilog HDL or VHDL files to the project and specify the top level entity
to be multichannel_example .
4. On the Tools menu, click MegaWizard Plug-In Manager . In the MegaWizard
Plug-In Manager dialog box, select Edit an existing custom megafunction
variation and select the nco.vhd file with Megafunction name NCO v10.1 .
5. Click Next to display IP Toolbench, Click Parameterize to review the parameters,
then click Generate .
6. Open ModelSim, and change the directory to the appropriate multiple channel
example design verilog or vhdl directory.
7. Select TCL > Execute Macro from the Tools menu in ModelSim. Select the
multichannel_example_ver_msim.tcl script for the Verilog HDL design or the
multichannel_example_vhdl_msim.tcl script for the VHDL design.
8. Observe the behavior of the design in the ModelSim Wave window.
The oscillator meets the following specifications:
■
■
■
■
■
SFDR: 110 dB
Output Sample Rate: 200 MSPS (50 MSPS per channel)
Output Frequency: 5MHz, 2MHz, 1MHz, 500KHz
Output Phase: 0, ? /4, ? /2, ?
Frequency Resolution: 0.047 Hz
The design operates with a 200MHz clock rate and the number of channels option set
to 4. This means that the resulting waveforms have an output sample-rate of f clk /4.
Therefore, the maximum output clock frequency is 50MHz. In this case, the output
signal would have only one sample for a cycle. Figure A–2 shows the timing
relationship between Avalon-ST signals, a generated multiplexed signal stream and
de-multiplexed signal streams.
Figure A–2. Multi-Channel NCO Output Signals
clk
v alid
sin_o
A0
B0
C0
D0
A1
B1
C1
D1
A2
B2
C2
D2
startofpacket
endofpacket
sin_ch0
sin_ch1
sin_ch2
sin_ch3
NCO MegaCore Function
User Guide
A0
B0
C0
D0
A1
B1
C1
D1
November 2013 Altera Corporation
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