参数资料
| 型号： | IP-NCO |
| 厂商： | Altera |
| 文件页数： | 43/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 初始许可证 |
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Chapter 4: Functional Description
Functional Description
Figure 4–7 shows the timing diagram for a serial CORDIC NCO architecture.
Figure 4–7. Serial CORDIC Timing Diagram
clk
clken
phi_inc_i 31457
reset_n
out_ v alid
4–11
fsin_0 0
3
1404
2043
1574
257
-1201
-2011
fcos_0 0
2047
2046
1490
129
-1308
-2030
-1657
-383
1
Note that the fsin_0 and fcos_0 values can change while out_valid is low.
After the clock enable is asserted, the oscillator outputs sinusoidal samples at a rate of
one sample per N clock cycles, where N is the magnitude precision set in the NCO
MegaCore function. Figure 4–7 shows the case where N = 8. There is also an initial
latency of L clock cycles; the exact value of L depends on the parameters that you set.
Table 4–3 shows typical latency values for the different architectures.
Table 4–3. Latency Values
Latency
(2) , (3)
Architecture
Variation
Base
Minimum
Maximum
Small ROM
Large ROM
Multiplier-Based
all
all
Throughput = 1, Logic cells
7
4
11
7
4
11
13
10
17
Multiplier-Based
Throughput = 1, Dedicated, Special case
(1)
8
8
14
Multiplier-Based
Multiplier-Based
Throughput = 1, Dedicated, Not special case
Throughput = 1/2
10
15
10
15
16
26
CORDIC
CORDIC
Parallel
Serial CORDIC
2N + 4
2N + 2
20
18
(4)
(4)
74
258
(5)
(5)
Notes for Table 4–3 :
(1) Special case: (9 <= N <= 18 && WANT_SIN_AND_COS).
(2) Latency = base latency + dither latency+ frequency modulation pipeline + phase modulation pipeline (× N for serial CORDIC).
(3) Dither latency = 0 (dither disabled) or 2 (dither enabled).
(4) Minimum latency assumes N = 8.
(5) Maximum latency assumes N = 32
November 2013
Altera Corporation
NCO MegaCore Function
User Guide
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