参数资料
型号: IP-NCO
厂商: Altera
文件页数: 41/54页
文件大小: 0K
描述: IP NCO COMPILER
标准包装: 1
系列: *
类型: MegaCore
功能: 数控振荡器编译器
许可证: 初始许可证
Chapter 4: Functional Description
4–9
Functional Description
Frequency Hopping
The NCO MegaCore function supports frequency hopping in all architectures except
the serial CORDIC architecture. Frequency hopping allows control and configuration
of the NCO MegaCore function at run time so that carriers with different frequencies
can be generated and held for a specified period of time at specified slot intervals.
The MegaCore function supports multiple phase increment registers that you can
load using an Avalon-MM bus. You select the phase increment register using an
external hardware signal; changes on this signal take effect on the next clock cycle.
The maximum number of phase increment registers is 16.
1
During frequency hopping, the phase of the carrier should not experience
discontinuous change. Discontinuous carrier phase changes may cause spectral
emission problems.
Figure 4–4 shows the frequency hopping implementation.
Figure 4–4. Frequency Hopping Block Diagram
freq_sel_sig
address
phi_inc_i
NCO MegaCore Function
Avalon-MM
Interface
write_sig
reset_n
RAM
16 to 1 phi_inc_i
MUX
fsin_0
clk
clken
Numerically
Controlled
fcos_o
reset_n
clk
Oscillator
out_valid
clken
The RAM stores all hopping frequencies. The RAM size is < width >×< depth >, where
< width > is the number of bits required to specify the phase accumulator value to the
precision you select in the parameter editor, and < depth > is the number of bands you
select in the parameter editor.
November 2013
Altera Corporation
NCO MegaCore Function
User Guide
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