参数资料
型号: IP-NCO
厂商: Altera
文件页数: 47/54页
文件大小: 0K
描述: IP NCO COMPILER
标准包装: 1
系列: *
类型: MegaCore
功能: 数控振荡器编译器
许可证: 初始许可证
A. Exa mple Multichannel Design
Multichannel Design
Often in a system where the clock frequency of the design is much higher than the
sampling frequency, it is possible to time share some of the hardware.
Consider a system with a clock frequency of 200 MHz and a sampling rate of 50 MSPS
(Megasamples per second). You can actually generate four complex sinusoids using a
single instance of the NCO MegaCore function. This example design demonstrates
how you can achieve this using the multi-channel feature.
Example design 3 generates four multiplexed and de-multiplexed streams of complex
sinusoids, which can be used in a digital up or down converter design ( Figure A–1 ).
Figure A–1. Multi-Channel NCO Example Design
A v alon-Streaming
Counter
out_ v alid
fsin_o
v alid
fsin_o
fcos_o
phi_ch0
phi_ch1
phi_inc_i
fcos_o
startofpacket
endofpacket
phi_ch2
phi_ch3
fmod_ch0
NCO
sin_ch0
sin_ch1
fmod_ch1
fmod_ch2
fmod_ch3
re q _mode_i
sin_ch2
sin_ch3
cos_ch0
pmod_ch0
pmod_ch1
pmod_ch2
pmod_ch3
phase_mod_i
cos_ch1
cos_ch2
cos_ch3
Counter
The design also generates five output signals ( valid , startofpacket , endfopacket ,
fsin_o and fcos_o ) that are used by the Avalon-ST interface as shown in Figure A–1 .
There are separate top-level design files (named multichannel_example.v and
multichannel_example.vhd ) for Verilog HDL and VHDL in the directories:
< IP install path >\nco\example_designs\multi_channel\verilog
< IP install path >\nco\example_designs\multi_channel\vhdl
To open the multichannel example design perform the following steps:
November 2013
Altera Corporation
NCO MegaCore Function
User Guide
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