参数资料
| 型号： | IP-NCO |
| 厂商： | Altera |
| 文件页数： | 42/54页 |
| 文件大小： | 0K |
| 描述： | IP NCO COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 数控振荡器编译器 |
| 许可证： | 初始许可证 |
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4–10
Chapter 4: Functional Description
Functional Description
Timing Diagrams
Figure 4–5 shows the timing with a single clock cycle per output sample.
Figure 4–5. Single-Cycle Per Output Timing Diagram
clk
clken
phi_inc_i 42949673
reset_n
fsin_0 0
-3 2057 41... 61.... 8148 10... 12... 13.... 15...
fcos_0 0
32767
32... 32... 32... 32... 31... 31... 30... 29... 28
out_ v alid
All NCO architectures—except for serial CORDIC and multi-cycle multiplier-based
architectures—output a sample every clock cycle. After the clock enable is asserted,
the oscillator outputs the sinusoidal samples at a rate of one sample per clock cycle,
following an initial latency of L clock cycles. The exact value of L varies across
architectures and parameterizations.
1
For the non-single-cycle per output architectures, the optional phase and frequency
modulation inputs need to be valid at the same time as the corresponding phase
increment value. The values should be sampled every 2 cycles for the two-cycle
multiplier-based architecture and every N cycles for the serial CORDIC architecture,
Figure 4–6 shows the timing diagram for a two-cycle multiplier-based NCO
architecture.
Figure 4–6. Two-Cycle Multiplier-Based Architecture Timing Diagram
clk
clken
phi_inc_i 85899346
reset_n
out_ v alid
fsin_0 0
-3 41... 81... 12.... 15... 19... 22... 25... 27... 29... 31... 32.... 32... 32... 32... 31... 29...
fcos_0 0
32766
32... 32... 31... 30... 28... 26... 23... 20... 17... 13... 10... 61.... 20... -2... -6... -1... -1...
After the clock enable is asserted, the oscillator outputs the sinusoidal samples at a
rate of one sample for every two clock cycles, following an initial latency of L clock
cycles. The exact value of L depends on the parameters that you set.
NCO MegaCore Function
User Guide
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
| IP-RIOPHY | IP RAPID I/O |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-NIOS | 功能描述:开发软件 Nios II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPO-002-VSF-LF | 制造商:PROXISTOR AB ELECTRONIC 功能描述:PROXIMITY SWITCH, PNP; Sensor Input:Inductive; Sensing Range Max:2mm; Supply Voltage DC Min:10V; Supply Voltage DC Max:30V; SVHC:No SVHC (19-Dec-2012); External Depth:10.5mm; External Length / Height:16.5mm; External Width:30mm; |
| IPOD TOUCH4-C-B | 制造商:Distributed By MCM 功能描述:Apple® iPod Black Touch 4th Gen Digitizer + Glass 制造商:Distributed By MCM 功能描述:APPLE IPOD TOUCH DIGITIZER BLACK |
| IPOD TOUCH4-C-W | 制造商:Distributed By MCM 功能描述:APPLE IPOD TOUCH DIGITIZER WHITE 制造商:Distributed By MCM 功能描述:Apple® iPod White Touch 4th Gen Digitizer + Glass |
| IPP015N04N G | 功能描述:MOSFET OptiMOS 3 PWR TRANST 40V 120A RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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