1169
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
Doc. Rev
6438E
Comments
Change
Request
Ref.
Introduction:
“Two Three-channel 32-bit Timer/Counters” peripheral feature changed into “Two Three-channel 16-bit
Timer/Counters” .
6828
ECC row added to Figure 6-1 “SAM9G45 Memory Mapping”
6842
Typos corrected in Table 8-1: AC97 --> AC97C (also in Table 24-1 and Table 41-1), PWMC --> PWM,
RNG --> TRNG (also in Figure 2-1 and Table 46-4)
RFO
Bus Matrix (MATRIX):
Figure 19-1 “DDR Multi-port”, and text above and below added.
1 row and 1 column added to Table 19-3 and Table 19-4.
6797
DDR/SDR SDRAM Controller (DDRSDRC):
“NO_OPTI” bit removed.
“DIS_ANTICIP_READ” description edited.
6871
Electrical Characteristics:
Section 46.14 “DDRSDRC Timings”, list of
Supported speed grade limitations updated.
6776
Section 46.11 “Touch Screen ADC (TSADC)”, TTH (ns) formula edited.
Last sentence in the Note added.
6800
RFO
SPI Master Mode figure titles reversed between Figure 46-5 and Figure 46-6.
SPI Master and Slave Mode figure titles edited again, from Figure 46-5 “SPI Master Mode 1 and 2” to
Figure 46-8 “SPI Slave Mode 1 and 2”
6847
6872
Table 46-2 ‘DC Characteristics’, I
SC values changed.
6903
Ethernet MAC 10/100 (EMAC):
Wake-on-LAN feature activated, including Section 35.4.12 “Wake-on-LAN Support” and Section 35.6.26
“Wake-on-LAN Register”.
EMAC interrupt on Wake-on-LAN Event activated.
6836
6838
Peripheral DMA Controller (PDC):
Typos corrected in Table 24-1: AC97 --> AC97C and TSDAC --> TSADCC
RFO
Power Management Controller (PMC):
Section 26.12.13 “PMC Programmable Clock Register”, CSS and SLCMCK fields edited.
6844
Universal Synchronous Asynchronous Receiver Transmitter (USART):
Section 33. “Universal Synchronous Asynchronous Receiver Transmitter (USART)”, SPI feature added.
6837