129
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
19. Bus Matrix (MATRIX)
19.1
Description
The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths
between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix
interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is
one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration
User Interface with Registers that allow the Bus Matrix to support application specific features.
19.2
Embedded Characteristics
12-layer Matrix, handling requests from 11 masters
Programmable Arbitration strategy
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master or fixed default
master
Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
One Address Decoder provided per Master
Boot Mode Select
– Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
– Selection is made by General purpose NVM bit sampled at reset
Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External
Flash)
– Allows Handling of Dynamic Exception Vectors
19.2.1
Matrix Masters
The Bus Matrix of the SAM9G45 manages Masters, thus each master can perform an access concurrently with
others, depending on whether the slave it accesses is available.
Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the
addressing, all the masters have the same decodings.
Table 19-1.
List of Bus Matrix Masters
Master 0
ARM926 Instruction
Master 1
ARM926 Data
Master 2
Peripheral DMA Controller (PDC)
Master 3
USB HOST OHCI
Master 4
DMA
Master 5
DMA
Master 6
ISI Controller DMA
Master 7
LCD DMA