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166
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
User Interface in the Bus Matrix Section.) Access to an external CompactFlash device is then made by accessing
the address space reserved to NCS4 and/or NCS5 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and
between 0x6000 0000 and 0x6FFF FFFF for NCS5).
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals
_IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.
I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode
Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, com-
mon memory mode, attribute memory mode and True IDE mode.
The different modes are accessed through a specific memory mapping as illustrated on
Figure 20-5. A[23:21] bits
Figure 20-5. CompactFlash Memory Mapping
Note:
The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode).
CFCE1 and CFCE2 Signals
To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd
byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the
corresponding NCS pin (NCS4 or NCS5). The Chip Select Register (DBW field in the corresponding Chip Select
Register) of the NCS4 and/or NCS5 address space must be set as shown in
Table 20-7 to enable the required
access type.
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select
mode on the corresponding Chip Select.
CF Address Space
Attribute Memory Mode Space
Common Memory Mode Space
I/O Mode Space
True IDE Mode Space
True IDE Alternate Mode Space
Offset 0x00E0 0000
Offset 0x00C0 0000
Offset 0x0080 0000
Offset 0x0040 0000
Offset 0x0000 0000
Table 20-6.
CompactFlash Mode Selection
A[23:21]
Mode Base Address
000
Attribute Memory
010
Common Memory
100
I/O Mode
110
True IDE Mode
111
Alternate True IDE Mode