![](http://datasheet.mmic.net.cn/20000/MQ83C154CXXX-30P883R_datasheet_1389815/MQ83C154CXXX-30P883R_47.png)
47
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data
for cache line eviction or cleaning of dirty cache lines.
The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer opera-
tions are closely connected as their configuration is set in each section by the page descriptor in the MMU
translation table.
9.7.2.2
Write Buffer
The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buf-
fer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid
stalling the processor when writes to external memory are performed. When a store occurs, data is written to the
write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed
(typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks.
DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each
section and page descriptor within the MMU translation tables.
9.7.2.3
Write-though Operation
When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer
which transfers it to external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.
9.7.2.4
Write-back Operation
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-
to-date with those in the external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.