1064
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
45.6.2.8
Timegen
The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC, LCDDEN, and
LCDMOD, used by the LCD module. This block is programmable in order to support different types of LCD mod-
ules and obtain the output clock signals, which are derived from the LCDC Core clock.
The LCDMOD signal provides an AC signal for the display. It is used by the LCD to alternate the polarity of the row
and column voltages used to turn the pixels on and off. This prevents the liquid crystal from degradation. It can be
configured to toggle every frame (bit MMODE = 0 in LCDMVAL register) or to toggle every programmable number
of LCDHSYNC pulses (bit MMODE = 1, number of pulses defined in MVAL field of LCDMVAL register).
Figure 45-3. Full Frame Timing, MMODE=1, MVAL=1
Figure 45-4. Full Frame Timing, MMODE=0
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through
LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL
field of LCDCON1 register controls the rate of this signal. The divisor can also be bypassed with the BYPASS bit in
the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The
minimum period of the LCDDOTCK signal depends on the configuration. This information can be found in
TableThe LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2
register:
Always Active (used with TFT LCD Modules)
Active only when data is available (used with STN LCD Modules)
f
LCD_MOD
f
LCD_HSYNC
2
MVAL
1
+
()
×
----------------------------------------
=
LCDVSYNC
LCDMOD
LCDDOTCK
Line1
Line2
Line3
Line4
Line5
LCDVSYNC
LCDMOD
LCDDOTCK
Line1
Line2
Line3
Line4
Line5
f
LCDDOTCK
f
LCDC_clock
CLKVAL
1
+
--------------------------------
=