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SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
21.13 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the
SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4,
8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always
aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the
address of the page in memory, the LSB of address define the address of the data in the page as detailed in
TableWith page mode memory devices, the first access to one page (t
pa) takes longer than the subsequent accesses to
the page (t
sa) as shown in Figure 21-34. When in page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page.
Notes:
1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
21.13.1
Protocol and Timings in Page Mode
Figure 21-34 shows the NRD and NCS timings in page mode access.
Figure 21-34. Page Mode Read Protocol (Address MSB and LSB are defined in
Table 21-6)
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup
and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length
Table 21-6.
Page Address and Data Address within a Page
Page Size
Page Address(1)
Data Address in the Page(2)
4 bytes
A[25:2]
A[1:0]
8 bytes
A[25:3]
A[2:0]
16 bytes
A[25:4]
A[3:0]
32 bytes
A[25:5]
A[4:0]
A[MSB]
NCS
MCK
NRD
D[31:0]
NCS_RD_PULSE
NRD_PULSE
tsa
tpa
tsa
A[LSB]