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SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled
first. The parameters can then be modified. Once this has been done, the user must re-enable the programma-
ble clock and wait for the PCKRDYx bit to be set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
6.
Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via
registers PMC_PCER and PMC_PCDR.
Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a
clear view as to which peripheral clock is enabled.
Note:
Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
26.11 Clock Switching Details
26.11.1
Master Clock Switching Timings
Table 26-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another
one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64
clock cycles of the new selected clock has to be added.
Table 26-1.
Clock Switching Timings (Worst Case)
From
Main Clock
SLCK
PLLA Clock
To
Main Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLLA Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLLA Clock +
5 x SLCK
PLLA Clock
0.5 x Main Clock +
4 x SLCK +
PLLACOUNT x SLCK +
2.5 x PLLAx Clock
2.5 x PLLA Clock +
5 x SLCK +
PLLACOUNT x SLCK
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK