参数资料
型号: IPT-C2H-NIOS
厂商: Altera
文件页数: 61/138页
文件大小: 0K
描述: C2H COMPILER FOR NIOS II
标准包装: 1
系列: Nios®II
类型: Nios II
功能: C 到硬件编译器
许可证: 初始许可证
C-to-Hardware Mapping Reference
Each of these signals is registered at the master port interface of the
hardware accelerator. Logic within the accelerator synchronizes these
signals to produce coherent Avalon-MM master transfers at the master
port.
Address Computation
Consider the pointer dereference in the following code which performs a
read operation:
int j = *(ptr_to_int + i);
The C2H Compiler generates logic of the following form to compute the
address signal:
ptr_to_int_i_addr = ptr_to_int + i * sizeof(int);
Figure 3–9 shows an example of the logic created for this pointer
dereference for a read operation.
Figure 3–9. Address Generation for a Read Operation
In Figure 3–9 , first, the address expression is evaluated. Assuming
sizeof(int) is 4, i must be multiplied by four, which is equivalent to
left-shifting by 2 bits. Bitwise shift operators require no logic elements to
compute, and the result is not registered. (See section “Unregistered
Operations and Assignments” on page 3–3 .) The signal
ptr_to_int_i_address feeds registers that drive the address signals
on the Avalon-MM master port. As soon as the address signal
ptr_to_int_i_address is valid, read-enable control logic asserts the
signal ptr_to_int_i_read , which initiates a transfer on the master
Altera Corporation
November 2009
9.1
3–21
Nios II C2H Compiler User Guide
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